fixes a couple of arm-embedded stuff,
adds some controllers, start of fpv4_s16 support, for a complete list of
changes see below:
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r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line
Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
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r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line
Fixed flags detections code for wide->short optimization code for Thumb-2
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r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
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r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line
Added register specifications to lpc1768.pp. From Joan Duran
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r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines
Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
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r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line
Added all STM32F1 configurations
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r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line
Added initial support for the Cortex-M4F FPv4_S16 FPU
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r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line
Added FPv4_d16 FPU instructions, and a few extra registers
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r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
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r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines
Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
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r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines
Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
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r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines
Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
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r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
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r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines
Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)
git-svn-id: trunk@22792 -
fix the double running of second_pass in the way it was intended to work: check for left.expectloc instead of left.location.loc
git-svn-id: trunk@22788 -
x86_64 is the most elaborated, has some degree of indirect function (GNU_IFUNC) and TLS support, so it is even able to link with static libc/pthreads code (tw14265) and produce an executable that can launch (but still fails due to invalid DWARF unwind info).
i386 produces working shared libraries if they are compiled with -Cg, without one your mileage may vary. tw14265 does not link yet due to missing COMDAT group support.
git-svn-id: trunk@22775 -
registers like the M68k): check whether the register type of the base/index register
of the instruction's reference is the same as the one we are doing register allocation
for. Otherwise the address registers can become corrupted.
git-svn-id: trunk@22748 -
* enable the 6 parameter syscall variant (still everything dummied out though)
* add termios constants
* don't change signal handlers for now
* disable assembly set routines as set handling was changed
git-svn-id: trunk@22743 -
(of which the names had changed from FPC_MUL_LONGWORD->FPC_MUL_DWORD and FPC_MOD_CARDINAL->
FPC_MOD_DWORD).
Also disable the usage of FPU opcodes for Coldfire.
git-svn-id: trunk@22739 -
M68000 CPUs they are nevertheless more restricted in some cases, so these need to be
handled explicitely (especially if symbols are involved).
git-svn-id: trunk@22738 -
* generate special return code for non-68020 CPU which don't support RTD instruction (based on
out code a few lines further down)
git-svn-id: trunk@22736 -
It seems that GNU as needs the syntax "offset(register.size*scale)" if the base address
register is ommited instead of "offset(,register.size*scale)". Now the System unit
assembles and nearly the complete RTL can be built.
git-svn-id: trunk@22734 -
leave "and" and "or" as "and" and "or" as according to the assembly language reference the
assembler should automatically choose the correct instruction (though Coldfire still should
be tested for ORI/ANDI to CCR
git-svn-id: trunk@22733 -
