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Author SHA1 Message Date
joost
16b44b0719 * Allow longer package-names as fpmake-dependencies. Addins could have longer names 
git-svn-id: trunk@36088 -
 2017-05-04 20:21:27 +00:00
nickysn
aa93259463 + support the lahf,fstsw and fnstsw instructions in 
TX86AsmOptimizer.RegLoadedWithNewValue

git-svn-id: trunk@36087 -
 2017-05-04 16:02:01 +00:00
yury
2ae3ce79bb * ARM: Never use the "BLX label" instruction. Use "BL label" instead. 
The linker will always change BL to BLX if necessary, but not vice versa (linker version dependent).
  "BLX label" ALWAYS changes the instruction set. It changes a processor in ARM state to Thumb state,
  or a processor in Thumb state to ARM state.

git-svn-id: trunk@36086 -
 2017-05-04 15:55:55 +00:00
Mattias Gaertner
a358fec12b pastojs: use UsesClause instead of UsesList 
git-svn-id: trunk@36085 -
 2017-05-04 15:54:42 +00:00
Mattias Gaertner
91ed2c4d9d fcl-passrc: resolver type alias with dotted unit name 
git-svn-id: trunk@36084 -
 2017-05-04 15:54:12 +00:00
nickysn
92cc447326 + support the aam instruction in TX86AsmOptimizer.RegLoadedWithNewValue 
git-svn-id: trunk@36083 -
 2017-05-04 15:34:48 +00:00
nickysn
2431b1fa19 + support the lodsb,lodsw,lodsd and lodsq instructions in 
TX86AsmOptimizer.RegLoadedWithNewValue

git-svn-id: trunk@36082 -
 2017-05-04 15:12:37 +00:00
nickysn
6b7593d7d0 + support the SETcc instructions in TX86AsmOptimizer.RegLoadedWithNewValue 
git-svn-id: trunk@36081 -
 2017-05-04 14:43:18 +00:00
nickysn
0cd70844f1 + take into account the fact that lea doesn't read the segment register of its 
reference in i386's TCpuAsmOptimizer.RegReadByInstruction

git-svn-id: trunk@36080 -
 2017-05-04 14:13:53 +00:00
nickysn
e10f184b74 + support lds,les,lfs,lgs and lss in TX86AsmOptimizer.RegLoadedWithNewValue 
git-svn-id: trunk@36079 -
 2017-05-04 14:08:36 +00:00
nickysn
9b7a8f0da5 + take into account the x86 segment register in TAOptBase.RegInRef 
git-svn-id: trunk@36078 -
 2017-05-04 14:08:00 +00:00
nickysn
eac74f5a81 + support the cwd,cdq,cqo and cbw instructions in 
TX86AsmOptimizer.RegLoadedWithNewValue (cwde and cdqe don't need special
  support)

git-svn-id: trunk@36077 -
 2017-05-04 12:15:40 +00:00
yury
95094e9a8f * Removed unused vars. 
git-svn-id: trunk@36073 -
 2017-05-04 10:38:49 +00:00
joost
50fea20003 * Add FPMake-plugin dependencies to unit path + test 
git-svn-id: trunk@36072 -
 2017-05-03 20:34:55 +00:00
nickysn
987cf2a9cf * fixed a bug in the maxqword check in the Rol/RorQWord(maxqword,x)->maxqword 
optimization, which prevented the optimization from ever being performed. This
  should also fix the test failure of tbs/tb0627b.pp on all 64-bit platforms.

git-svn-id: trunk@36071 -
 2017-05-03 15:32:48 +00:00
Mattias Gaertner
8ad6588e46 pastojs: fixed tests 
git-svn-id: trunk@36070 -
 2017-05-03 15:26:22 +00:00
Mattias Gaertner
bf9dffbaf8 fcl-passrc: pasresolver: resolve dotted unit names and default program namespace 
git-svn-id: trunk@36069 -
 2017-05-03 15:26:06 +00:00
nickysn
1a139b951d + properly support the one operand version of imul and mul in 
TX86AsmOptimizer.RegLoadedWithNewValue

git-svn-id: trunk@36068 -
 2017-05-03 15:07:21 +00:00
nickysn
65960048c8 * fixed TX86AsmOptimizer.RegLoadedWithNewValue for 3-operand imul, where the 
second operand is a memory reference

git-svn-id: trunk@36067 -
 2017-05-03 13:43:16 +00:00
nickysn
1f5aec6d3d + make use of the Reg1WriteOverwritesReg2Entirely and Reg1ReadDependsOnReg2 
instead of SuperRegistersEqual in TX86AsmOptimizer.RegLoadedWithNewValue, so
  it returns correct information for the 16-bit and 8-bit subregisters
  (including AH,BH,CH and DH)

git-svn-id: trunk@36066 -
 2017-05-03 12:14:30 +00:00
nickysn
c096b1fe6b * fixed the debug output, generated by -dDEBUG_INSTRUCTIONREGISTERDEPENDENCIES 
for x86 instructions, entered via inline assembler, using intel syntax
  (the low level optimizer isn't normally run on them, so it doesn't matter that
  InstructionLoadsFromReg and similar functions don't work on them, but with
  -dDEBUG_INSTRUCTIONREGISTERDEPENDENCIES it is much more convenient for
  debugging purposes to have correct data for them, because you can enter
  instructions manually and see how these functions behave)

git-svn-id: trunk@36065 -
 2017-05-03 10:14:35 +00:00
florian
bfca9d3477 * avr I/O space is always shifted by 32 bytes in memory 
git-svn-id: trunk@36064 -
 2017-05-02 19:51:22 +00:00
florian
39b7f1bffe * do not write assembler optimizer debug output in avr assembler files 
git-svn-id: trunk@36063 -
 2017-05-02 19:50:37 +00:00
michael
6d4d053744 * Correct bugtraq url 
git-svn-id: trunk@36062 -
 2017-05-02 17:17:12 +00:00
michael
dff39e9ecb * Fix test case 
git-svn-id: trunk@36060 -
 2017-05-02 14:03:56 +00:00
nickysn
881cb790a9 + added tests that check side effect removal behaviour for the simplifications 
added/changed today

git-svn-id: trunk@36053 -
 2017-05-01 21:01:26 +00:00
nickysn
7821d729cd + a very basic test for correctness for the various simplifications, implemented 
today. It does not check for side effects and thus it should work at any
  optimization level, regardless of whether each optimization is done or not.

git-svn-id: trunk@36048 -
 2017-05-01 20:17:07 +00:00
nickysn
f65f0b125a + optimize sar(0,x) to 0 and sar(-1,x) to -1 
git-svn-id: trunk@36044 -
 2017-05-01 19:12:04 +00:00
nickysn
c028362f31 * added the missing pop directive after the push directive in handle_const_rox 
git-svn-id: trunk@36043 -
 2017-05-01 18:25:01 +00:00
nickysn
855cd616f0 + optimize rol(0, x) and ror(0, x) to 0; also optimize the case with all ones, 
e.g. rol32(ffffffff, x) = ffffffff, etc.

git-svn-id: trunk@36042 -
 2017-05-01 18:19:49 +00:00
nickysn
de1e0c405e + optimize '0 shl x' and '0 shr x' to 0 
git-svn-id: trunk@36041 -
 2017-05-01 18:16:38 +00:00
nickysn
546e993c25 * use resultdef for the type of the resulting zero const from the '0*x' and 
'0 and x' optimization

git-svn-id: trunk@36040 -
 2017-05-01 18:11:12 +00:00
nickysn
f26a844b19 * only do the '0*x' and '0 and x' optimization if x has no side effects (except 
at -O4, where it is done regardless of whether there are side effects or not)

git-svn-id: trunk@36039 -
 2017-05-01 17:34:19 +00:00
Mattias Gaertner
142d95e0d2 pastojs: implemented SetLength(string,int) 
git-svn-id: trunk@36037 -
 2017-05-01 14:36:30 +00:00
nickysn
e79f49a2b4 + mask only the low bits that matter for the const of OP_ROL and OP_ROR in 
tcg.optimize_op_const()

git-svn-id: trunk@36036 -
 2017-05-01 14:18:37 +00:00
Mattias Gaertner
a4e26a7222 pastojs: implemented inc/dec for var/out arg 
git-svn-id: trunk@36035 -
 2017-05-01 13:32:30 +00:00
nickysn
f44f2f9194 * do the optimizations in r36027 at level -O3 or higher 
git-svn-id: trunk@36034 -
 2017-05-01 13:14:32 +00:00
nickysn
6d589f415b * do the left.equals(right) check before might_have_sideeffects, because 
left.equals(right) is usually faster

git-svn-id: trunk@36033 -
 2017-05-01 12:57:15 +00:00
nickysn
056e742684 + enable the internal 8-bit and 16-bit sar on i8086 
git-svn-id: trunk@36032 -
 2017-05-01 12:36:36 +00:00
nickysn
29429cca3c + mask the shift/rotate count value in the rol/ror/sar inline nodes, before 
checking for 0, so that things like sar(int32,32) can be optimized to int32,
  just like sar(int32,0)

git-svn-id: trunk@36031 -
 2017-05-01 11:45:23 +00:00
nickysn
217d39abf1 * fixed bug in r36027 (I had it fixed already, but accidentally committed the 
wrong file in r36027)

git-svn-id: trunk@36030 -
 2017-05-01 11:43:16 +00:00
nickysn
5aeb73b940 + optimizations (at -O2 level) for (where 'a' is an integer expression, without 
side effects):
  * a - a   -> 0
  * a xor a -> 0
  * a and a -> a
  * a or a  -> a
  * a <> a  -> false
  * a < a   -> false
  * a > a   -> false
  * a = a   -> true
  * a <= a  -> true
  * a >= a  -> true

git-svn-id: trunk@36027 -
 2017-05-01 10:17:50 +00:00
nickysn
ed984e0c76 - removed missing file from project 
+ compile with the EXTDEBUG define to catch more errors

git-svn-id: trunk@36025 -
 2017-04-30 20:48:35 +00:00
nickysn
b17d97050f + also simplify rol(x,0) and ror(x,0) to x 
git-svn-id: trunk@36024 -
 2017-04-30 20:45:51 +00:00
nickysn
8ac84ce43a + simplify sar(x,0) to x 
git-svn-id: trunk@36023 -
 2017-04-30 20:24:44 +00:00
nickysn
d8ec0eff8e + implemented inline code generation for 64-bit sar (the SarInt64 intrinsic) on 
less-than-64-bit CPUs that have a 64-bit OP_SHR/OP_SHL/OP_SAR implementation
  in their cg64 backend code generator. This is enabled only for i386 for now.

git-svn-id: trunk@36022 -
 2017-04-30 16:06:34 +00:00
nickysn
4e4e5d6d07 + allocate and free the flags register (when necessary), when generating code 
for OP_SHR,OP_SHL and OP_SAR in tcg64f8086.a_op64_const_reg

git-svn-id: trunk@36021 -
 2017-04-30 01:25:54 +00:00
Károly Balogh
a25912da0d fcl-passrc: fixed build broken since r36006 
git-svn-id: trunk@36020 -
 2017-04-29 22:56:12 +00:00
Károly Balogh
01ebb52ba8 morphos: added tf_needs_smybol_type and tf_needs_symbol_size flags. fixes generated executables to not be falsely recognized as PowerUP but native binaries 
git-svn-id: trunk@36019 -
 2017-04-29 22:31:41 +00:00
nickysn
b8c4dd9e18 + implemented 64-bit OP_SHR,OP_SHL and OP_SAR in a_op64_reg_reg for i8086 and 
use it in the shl/shr node for code generation.

git-svn-id: trunk@36018 -
 2017-04-29 21:57:48 +00:00