m68k/cgcpu.pas, tcg68k:
+ override g_adjust_self_value as we don't do register allocation for the wrapper we need to adjust the Self value using the scratch registers (could be improved however) and we also can not use the offset that the original procedure in tcg uses
* fix g_intf_wrapper by using the correct operations and loading the correct (virtual) method offset
git-svn-id: trunk@25728 -
m68k/cgcpu.pas, tcg68k:
- remove g_save_registers and g_restore_registers which DID NOT CALL inherited!
- also remove commented methods g_save_all_registers & g_restore_all_registers
git-svn-id: trunk@25715 -
- removed the ancient DEBUG_CHARLIE silliness... :)
- moved some repeated code patterns into separate functions
- rewrote most of of tcg68k.a_op_const_reg and tcg68k.a_op_reg_reg
- smarter code generation in tcg68k.a_cmp_const_reg_label
- added support for MULU/MULS on Coldfire in a case which is often used by the CG to index arrays to be used instead of the RTL helpers, this results in a *HUGE* speedup in tw5086 for example
git-svn-id: trunk@25702 -
cgobj.pas, tcg:
* g_save_registers: add the amount of used address registers to size as well
* g_save_registers: save all used address registers
* g_restore_registers: restore all stored address registers
m68k/cpubase.pas:
* rename saved_standard_address_registers to saved_address_registers
all other platform's cpubase.{inc,pas} (except alpha, ia64 and vis which are not up to date):
* add a saved_address_registers variable with one entry of RS_INVALID
At least a "make fullcycle" did complete.
git-svn-id: trunk@25664 -
m68k/cgcpu.pas, tcg68k.g_proc_exit:
* use A0 (which is a volatile register) instead of A3 (which is not) to restore the stack pointer
git-svn-id: trunk@25663 -
this fixes varargs a bit, particularly fixes an unhandled TList bounds exception while compiling packages/fcl-base/src/eventlog.pp
git-svn-id: trunk@25636 -
paramgr.pas, tparamanager:
+ add virtual get_volatile_registers_address method which by default returns an empty set
cgobj.pas, tcg:
* allocallcpuregisters: also allocate address registers if needed
* deallocallcpuregisters: also deallocate address registers if needed
ncgcal.pas, tcgcallnode.pass_generate_code:
* (de)allocate address registers
* keep result from being deallocated if it should be an address register (currently by no architecture...)
m68k/cpupara.pas, tm68kparamanager:
+ get_volatile_registers_address: return a0 and a1 as volatile registers
m68k/n68kmat.pas, tm68kmoddivnode.call_rtl_divmod_reg_reg:
* (de)allocate address registers
git-svn-id: trunk@25633 -
m68k/n68kadd.pas, tn68kadd.second_cmpordinal:
* use the size of the largest operand to select a fiting operand
* ToDo: check whether a sign/zero extend of the value is necessary
git-svn-id: trunk@25628 -
m68k/n68kcnv.pas, tn68kcnv.second_int_to_bool:
* we need to check both the upper and the lower register for a 64-bit value to decide whether it's True or False
git-svn-id: trunk@25625 -
m68k/cgcpu.pas, tcg68k:
* a_load_ref_cgpara: use pashsize instead of paraloc^.size as the latter could be OS_NO and thus a "move" instead of a "move.x" will be generated resulting in a word move when a long or byte move might have been necessary
* a_load_reg_ref: use the smallest size when moving the value to a reference
* a_load_ref_ref: when the size is different always use a temporary register for a ref to ref move
* a_load_ref_ref: when doing a fixed move for Coldfire use the correct ref (that's another embarrasing error...) and size (fixes usage of String[Index] for a const array parameter)
* a_load_ref_reg: use the smallest size when moving the value from a reference
* g_concatcopy: don't use source.alignment as that doesn't contain the correct value and also load the value into the temp register using the correct size (fixes passing of small values as parameters, like chars)
git-svn-id: trunk@25624 -
m68k/cgcpu.pas, tcg68k.g_flags2reg:
* don't sign extend the flag value which was stored to the register, but instead do a "AND 1" on it to reduce it to 1 bit; afterall Booleans in Pascal are either 0 or 1 and not 0 or $FF
+ added test
git-svn-id: trunk@25598 -
Therefor the cpu type (-Cp...) "coldfire" was split up into "isaa", "isaa+", "isab" and "isac". The Linux RTL can currently compiled for "68020", "isab" and "isac". For the other three Bcc.L must be handled differently (only Bcc.B/W supported) and for "68000" also EXT.L needs to be handled differently.
fpcdefs.inc:
+ define CPUCAPABILITIES if capabilities can be set for a certain CPU type (currently ARM, AVR and M68k)
options.pas:
* check for CPUCAPABILITIES instead of specific CPUs
assemble.pas:
- the handling of the CPU type is already done in m68k/ag68kgas.pas, Tm68kGNUAssembler.MakeCmdLine (and thereby already using the gascputypestr array!)
m68k/cpuinfo.pas:
- tcputype: remove "cpu_coldfire"
+ tcputype: add "cpu_isa_a", "cpu_isa_a_p", "cpu_isa_b" and "cpu_isa_c"
+ add "cpu_coldfire" constant which contains all Coldfire specific cpu types
* adjust "cputypestr" and "gascputypestr"
+ add tcpuflags and cpu_capabilities (DBRA restriction was checked with CPUCOLDFIRE, CAS/TAS will be needed for atomic operations and BRAL restriction was discovered during testing of new cpu types)
m68k/cgcpu.pas:
* adjust checks for "cpu_coldfire"
m68k/n68kadd.pas:
* don't use a BRA.L if it is not supported, but (at least for now) a BRA.W
aggas.pas:
* adjusted check for Coldfire
git-svn-id: trunk@25457 -
contains the tcgsize of the entire parameter rather than only of
what is left (-> calculate it from the remaining parameter length)
git-svn-id: trunk@24776 -
m68k/cgcpu.pas, tcg68k:
+ overload "a_loadfpu_ref_cgpara" and use the 64-bit code generator to pass Doubles if they are located in references
Fixes around nearly 100 tests.
git-svn-id: trunk@23597 -
* initialize paraloc^.size to OS_INT instead of leaving it at 0
This fixes tests/test/cg/ttryexc1.pp. The problem was that the raise node generated code which resulted in a word(!) move of the raised object's address to the stack location for fpc_raiseexception. This then resulted in an error when freeing the exception object.
git-svn-id: trunk@23465 -
m68k/aasmcpu.pas, taicpu.spilling_get_operation_type:
* add all Sxx instructions as "operand_write" instructions
m68k/n68kadd.pas, t68kaddnode.getresflags:
* use the correct operation in case of swapped nodes
m68k/cgcpu.pas, tcg68k.g_flags2reg:
- don't move a 0 to the register, because this will CLR it and thus the flags won't be valid anymore...
- NEG would have been the wrong operation (NOT would have been correct), but it isn't needed anyway...
* simplify the method by handling the address register case only when necessary
git-svn-id: trunk@23383 -
use the correct flag for the copy loop: we jump back to the copy code as long as the value is positive aka BPL instead of BMI
This fixes around 30 tests (it fixes a quite bit more, but now some other tests seem to be broken...)
git-svn-id: trunk@23373 -
that the type of the parameters can be determined automatically
o added compilerproc declarations for all helpers called in the compiler
via their assembler name, so we can look up the corresponding procdef
git-svn-id: trunk@23325 -
