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6fff181679
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873 Commits

Author SHA1 Message Date
Jeppe Johansen
6fff181679 Add support for TBB/TBH instructions. 
Precisize rules for selection of thumb instructions.
Add short-cut notation support for most simple Thumb2 instructions ( add r1,#4 instead of add r1,r1,#4 ).

git-svn-id: branches/laksen/armiw@29343 -
 2014-12-27 16:00:06 +00:00
Jeppe Johansen
71cdedea82 Add missing NOP, and B instruction forms. 
Move ThumbFunc flag from section to symbol.
Make .w forms optional the other way around. If .w is explicitly put on an instruction the assembler should always chose a wide form.

git-svn-id: branches/laksen/armiw@29341 -
 2014-12-27 13:23:02 +00:00
Jeppe Johansen
cc418eef74 Added unified assembler syntax mode so it can be selected with $ASMMODE. 
Fixed bug in Mov instruction.
Added initial scanning of IT/LastInIT detection for proper instruction selection.
Disabled "wide" format flag detection again for now.

git-svn-id: branches/laksen/armiw@29338 -
 2014-12-27 00:19:09 +00:00
Jeppe Johansen
6976af8365 Change .thumb_func to be an ait_directive instead of it's own tai type. 
git-svn-id: branches/laksen/armiw@29334 -
 2014-12-26 23:13:14 +00:00
Jeppe Johansen
9683102813 BL/BLX in thumb mode is a long composed instruction in Thumb as well as Thumb2 
git-svn-id: branches/laksen/armiw@29333 -
 2014-12-26 23:10:34 +00:00
Jeppe Johansen
9227a9fcf2 Reenable check for Wide format flag. 
git-svn-id: branches/laksen/armiw@29331 -
 2014-12-26 20:08:07 +00:00
Jeppe Johansen
5c3093a937 Add most non-VFP Thumb-2 instruction entries for the ARM internal writer. 
git-svn-id: branches/laksen/armiw@29329 -
 2014-12-26 18:35:15 +00:00
Jeppe Johansen
3cb9b30165 Added full 16-bit Thumb support to the ARM internal writer. 
git-svn-id: branches/laksen/armiw@29326 -
 2014-12-25 19:33:14 +00:00
Jeppe Johansen
0494f48bfc Fix capability matrix for ARMv5. It should not have thumb support. 
git-svn-id: branches/laksen/armiw@29287 -
 2014-12-14 16:49:28 +00:00
Jeppe Johansen
901275b4a1 Switch back to emitting BLX instructions and fix calculation of constant offsets(should rarely/never happen). 
Add missing fields to other elf targets.

git-svn-id: branches/laksen/armiw@29286 -
 2014-12-14 16:28:35 +00:00
Jeppe Johansen
b4a4dda4e5 Make sure to change BLX instructions back to BL when the target is not a Thumb function. 
git-svn-id: branches/laksen/armiw@29282 -
 2014-12-13 18:18:51 +00:00
Jeppe Johansen
fe0cdcfb2e Add a small function to handle encoding of CPU specific ELF flags. This is used to encode EABI version for ARM. 
git-svn-id: branches/laksen/armiw@29281 -
 2014-12-13 17:16:25 +00:00
Jeppe Johansen
6c4dbf5a84 Change emission of pre-reloc BLX to BL. 
git-svn-id: branches/laksen/armiw@29278 -
 2014-12-12 23:12:53 +00:00
Jeppe Johansen
387824c1ee Added some APSR register bitmask definitions. 
Fixed a bunch of instruction encodings by comparing bulks of handwritten tests to binutils assembled versions.
Fixed emission of regsets of S and D registers above 15.
Fixed assembler reader for RRX shiftmode.
There can be a size postfix after a condition code in UAL assembler syntax. This has been added to the assembler reader.

git-svn-id: branches/laksen/armiw@29277 -
 2014-12-12 22:23:44 +00:00
Jeppe Johansen
414bfba2b2 Emitted instruction was B instead of BL for BL/BLX. 
git-svn-id: branches/laksen/armiw@29262 -
 2014-12-11 22:11:10 +00:00
Jeppe Johansen
e8cb1e198d Forgot to rebuild instruction tables. 
git-svn-id: branches/laksen/armiw@29261 -
 2014-12-11 21:58:05 +00:00
Jeppe Johansen
0b5bcdf439 Modify fixup of BL/BLX instructions and ensure proper form is generated. 
git-svn-id: branches/laksen/armiw@29260 -
 2014-12-11 21:50:44 +00:00
Jeppe Johansen
284a4d9dd7 Encoding of preindexed LDRH/STRH opcodes was missing. 
git-svn-id: branches/laksen/armiw@29254 -
 2014-12-11 11:20:25 +00:00
Jeppe Johansen
b5cd9c048e Small fix for uninitialized variables causing warnings. 
git-svn-id: branches/laksen/armiw@29253 -
 2014-12-11 09:26:48 +00:00
Jeppe Johansen
eb3eaab54b Fix some small encoding bugs. 
git-svn-id: branches/laksen/armiw@29250 -
 2014-12-10 23:28:09 +00:00
Jeppe Johansen
9e5979e8be Implemented UAL syntax support in the ARM assembler reader. Can be toggled with a field for now, but not implemented yet. Still using pre-UAL syntax for now. 
Switched codegeneration of VFPv2 and VFPv3 to use UAL mnemonics and syntax.
Updated VFP code in RTL to use UAL syntax too.
Added preliminary ELF support for ARM.
Added support for linking of WinCE COFF files. Should work for with a standard ARMv4-I target.

git-svn-id: branches/laksen/armiw@29247 -
 2014-12-10 20:44:34 +00:00
Jeppe Johansen
d023c63ad0 Add a lot of instruction table entries and missing instructions for support of most ARM32 mode instructions from ARMv4 up ARMv7A. 
Add some VFP registers.
Rebuilt tables.
Added a lot of VFPv3 and Advanced SIMD(not supported yet) oppostfixes.
Implemented code in aasmcpu to generate binary code from the instructions. Only ARM32 supported so far.

git-svn-id: branches/laksen/armiw@29246 -
 2014-12-10 20:38:23 +00:00
Jeppe Johansen
3bc1db9612 Fixed breakage in the ARM peephole optimizer indirectly brought to light by r29189. 
git-svn-id: trunk@29191 -
 2014-12-01 14:39:40 +00:00
Jeppe Johansen
d04e988ff1 Make sure optimizer don't generate invalid assembler forms (LDRD and STRD). 
git-svn-id: trunk@29189 -
 2014-11-30 17:34:37 +00:00
florian
5c67fcc43f + change always floating point divisions into multiplications if they are a power of two, 
this is an exact operation so it is always allowed
* change only divisions by normal numbers into multiplications

git-svn-id: trunk@29085 -
 2014-11-16 20:47:38 +00:00
Tomas Hajny
3ee3542744 * boolean constant instead of IFDEFs for detection of microcontroller support 
git-svn-id: trunk@29052 -
 2014-11-10 12:34:59 +00:00
Jeppe Johansen
d3e91bb60c Fixed issue #26965. The peephole optimization didn't move a potential register deallocation to after the ldr instruction causing mov's to be removed. 
git-svn-id: trunk@28977 -
 2014-11-03 18:33:32 +00:00
sergei
a3c439c60f - No longer insert BlockStart markers into asmlists. The presence of these markers disrupts peephole optimizations and require additional checks all over the place, causing various workarounds/hacks (like TAsmList.Create_without_marker) to start building up. 
A more radical approach is to remove them altogether. Tested with i386-win32 (the oldest peephole optimizer), mips-linux (the newest one) and arm-linux (the most complex one) targets. The fallout was limited to two minor issues fixed in r28629 and r28708, respectively.

git-svn-id: trunk@28711 -
 2014-09-22 21:33:50 +00:00
sergei
d37e72dbf9 * ARM: instructions do modify the base register of pre/postindexed references. Report this fact in spilling_get_operation_type_ref and RegModifiedByInstruction functions. 
git-svn-id: trunk@28708 -
 2014-09-22 16:18:16 +00:00
sergei
b08ffa0a87 * ARM: fixed detecting Thumb-style jump tables in insertpcrelativedata() after r28546. 
git-svn-id: trunk@28702 -
 2014-09-21 01:59:25 +00:00
sergei
4a90d7e3de + ARM internal linker: very initial support for Thumb mode, helloworld-class programs compiled with "-Cparmv6m -CIthumb" can now run. 
git-svn-id: trunk@28697 -
 2014-09-19 22:33:37 +00:00
Károly Balogh
1b0a1f4508 ARM: mimic what GNU C does while calling the profiling mcount on ARM 
git-svn-id: trunk@28648 -
 2014-09-13 00:17:10 +00:00
Károly Balogh
739c66291d ARM: first naive attempt to get gprofiling work for arm-linux. (Work-In-Progress, but at least for me it doesn't explode) 
git-svn-id: trunk@28645 -
 2014-09-12 18:51:02 +00:00
florian
3f71b059e5 * improve ldr*/str* handling for arm thumb 
git-svn-id: trunk@28583 -
 2014-09-02 19:37:45 +00:00
florian
2fa7171a45 * generate AND for small set comparisons also when only set vars are involved using the cg class, so it works for arm thumb as well 
git-svn-id: trunk@28569 -
 2014-08-31 20:43:13 +00:00
florian
8a7c16327c * fixes reference handling for arm thumb and ldrh, not perfect yet 
git-svn-id: trunk@28568 -
 2014-08-31 18:00:10 +00:00
florian
81c717fc06 + implemented tthumbcgarm.g_external_wrapper in a way which does not destroy lr 
git-svn-id: trunk@28560 -
 2014-08-31 16:35:01 +00:00
florian
dffdde7d53 * fixes reference handling for arm thumb and ldrb, not perfect yet and other ldr/str types might need similiar fixes 
git-svn-id: trunk@28549 -
 2014-08-31 11:37:17 +00:00
florian
db01c50a4f * fixes jump table generate for arm thumb 
git-svn-id: trunk@28546 -
 2014-08-30 22:13:09 +00:00
florian
836a6e46ca * several issues with interface wrappers for thumb fixed 
git-svn-id: trunk@28542 -
 2014-08-30 20:38:26 +00:00
florian
97fc823e33 * generate AND for small set comparions using the cg class, so it works for arm thumb as well 
git-svn-id: trunk@28540 -
 2014-08-30 18:02:59 +00:00
florian
09728a9ae2 * improved r28534: LDR/STR on thumb do not support registers >r7 as destination/source 
git-svn-id: trunk@28538 -
 2014-08-30 12:13:00 +00:00
Károly Balogh
5a7b1f00cf ARM: Thumb is an ugly mess, but this at least makes fcl-image package to build with -Ooregvar. someone with more clue is welcomed to review and come up with a better patch. 
git-svn-id: trunk@28534 -
 2014-08-29 17:04:48 +00:00
Károly Balogh
09608a1c28 * fix warnings when compiling the compiler with DFA optimizer enabled on ARM 
git-svn-id: trunk@28498 -
 2014-08-20 13:16:58 +00:00
Jonas Maebe
e21d31dc99 * fixed compilation with range checking enabled 
git-svn-id: trunk@28447 -
 2014-08-18 20:06:27 +00:00
Jonas Maebe
5e280b3131 * don't convert movs into (the non-existing) ldrs in do_spill_replace() 
git-svn-id: trunk@28390 -
 2014-08-12 20:14:24 +00:00
masta
96915b3f0c 16bit Thumb is not able to use tst with an immediate value 
r28315 introduced an arm optimization which requires
  tst rX, #imm
to work. This is not available on 16bit thumb, I've disabled that
optimization on thumb for now.

git-svn-id: trunk@28360 -
 2014-08-10 15:30:44 +00:00
masta
7e22bd53b6 Changed ARMs StrLdr2StrMov peephole optimizer look further ahead 
StrLdr2StrMov now uses GetNextInstructionUsingRef to find an instruction
which uses the same Reference. In one of our internal testcases it
speeded up a function by 15% as fpc generated a lot of spilling.

git-svn-id: trunk@28344 -
 2014-08-08 15:31:10 +00:00
masta
bfa85218fa Introduce TCpuAsmOptimizer.GetNextInstructionUsingRef 
It's the counterpart to GetNextInstructionUsingReg and finds the next
instruction to use the same reference. By default it stops searching
when hitting a store instructions to avoid aliasing issues.

git-svn-id: trunk@28343 -
 2014-08-08 15:31:06 +00:00
masta
d1c5f89976 Make Next an Out-parameter in ARMs GetNextInstructionUsingReg 
The input to Next is not used, reflect that properly.

git-svn-id: trunk@28342 -
 2014-08-08 15:31:01 +00:00