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c433b740e4
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89 Commits

Author SHA1 Message Date
Rika Ichinose
c433b740e4 Add/actualize CPUX86_HAS_SSSE3. 2025-03-05 22:35:01 +01:00
florian
60690e379e * typo fixed 2024-12-08 11:14:37 +01:00
florian
5b54ab2040 + zen5 architecture for completeness 2024-12-07 22:23:35 +01:00
Rika Ichinose
1030f67fb4 Use IndexQWord_SSE41 directly if -Cp RTL compiled with supports SSE 4.1. 2024-07-21 08:40:12 +00:00
florian
860c32f833 + set CPUX86_HINT_BSX_DEST_UNCHANGED_ON_ZF_1 for suitable CPUs 2024-06-01 19:41:46 +02:00
florian
53459fed2b + CPUX86_HINT_BSX_DEST_UNCHANGED_ON_ZF_1 2024-05-24 23:17:07 +02:00
florian
b826ad8b7e + CPUX86_HINT_FAST_SHORT_REP_MOVS 
* use FPC_MOVE instead of rep movs if possible, partially fixes #40785
 2024-05-16 22:59:21 +02:00
florian
cad21584e5 + Skylake-X 2024-02-25 22:52:30 +01:00
florian
587af1c78e * icelake is x86-64-v4 2024-02-24 21:54:11 +01:00
florian
37ed03667f * fixed fpu_x86_64_v4_flags 2024-02-23 21:51:37 +01:00
J. Gareth "Curious Kit" Moreton
629c87efc8 * x86-64: Typo fixed in FPU type string array 2024-02-13 14:39:29 +00:00
J. Gareth "Curious Kit" Moreton
b4eabbe5ce * x86: Fixed CPU feature flags for AMD Jaguar and Piledriver 2024-02-06 22:15:51 +00:00
J. Gareth "Curious Kit" Moreton
e4bd58d66a * x86: Replaced CPU features array with "cpu_x86_64_v1_flags" where possible 2024-02-06 22:15:51 +00:00
florian
f80f1112d4 + Zen 4 2024-02-05 23:18:07 +01:00
florian
ac6dc582be + also add x86-64 as cpu type (gcc compatibility) 2024-02-03 22:40:54 +01:00
florian
f8dbb09a46 * fixed some issues with the x86-64 instruction versions 
* use more of the constants
 2024-02-01 22:08:27 +01:00
florian
ae465fa8dc + introduce x86-64 microarchitecture levels for cpu and fpu flags 2024-01-31 22:32:57 +01:00
florian
ff3b4adc27 + more CPU and FPU flags added 2024-01-30 22:55:42 +01:00
J. Gareth "Curious Kit" Moreton
ede47ffea9 * New "fast 3-component LEA hint" and "Icelake" CPU options 2023-10-29 10:26:52 +00:00
florian
9c10167b6f + CPUX86_HAS_BSWAP 2023-02-04 19:20:10 +01:00
J. Gareth "Curious Kit" Moreton
170c112301 * x86: Added FMA as an FPU target distinct from AVX and AVX2 (the latter of which has a new FPUX86_HAS_AVX2 flag) 2022-11-25 22:14:59 +00:00
J. Gareth "Curious Kit" Moreton
69c7838571 * x86: Addition of AMD CPUs: Bobcat, Jaguar, Piledriver, Excavator, Zen2 and Zen3 (and supporting flags) 2022-11-25 22:14:59 +00:00
J. Gareth "Curious Kit" Moreton
c9461b7313 * x86: Flags that relate to optimization hints rather than features have been moved to a separate set 2022-11-13 19:23:30 +00:00
J. Gareth "Curious Kit" Moreton
a0c87be0fc * x86: Zen processors now marked with CPUX86_HAS_FAST_BT_MEM flag 2022-11-12 13:18:53 +00:00
florian
d3abd339b7 + cpu switch for zen 2022-11-11 23:45:52 +01:00
J. Gareth "Curious Kit" Moreton
aa5517d442 * x86: New CPU feature flags in cpuinfo units 2022-11-11 22:29:58 +00:00
florian
27fb9086aa * cleanup: cs_opt_loopunroll is a generic optimization for a long time already 2022-03-08 23:03:18 +01:00
florian
ff3acfb8cd * cleanup of 2.7.0 defines 2021-10-31 13:20:28 +01:00
florian
468975aa30 + move often used floating point constants into registers 2021-09-05 18:19:58 +02:00
florian
c02b43fb93 * change fma cpu flag into an fpu flag 
git-svn-id: trunk@49448 -
 2021-06-01 21:16:52 +00:00
florian
b713c7380b * implemented UseAVX512 properly 
+ make use of VREDUCE* for frac(...) if AVX512QD is a available

git-svn-id: trunk@47840 -
 2020-12-23 17:25:09 +00:00
florian
a8b387a166 + make use of avx-512 instructions vcvtuis2s* if possible 
git-svn-id: trunk@47078 -
 2020-10-10 21:08:13 +00:00
florian
ef87879402 * common naming for fpu_none string 
git-svn-id: trunk@43768 -
 2019-12-24 16:14:28 +00:00
florian
ba203c0564 + x86 makes use of fpu_capabilities 
* moved CPUX86_HAS_AVXUNIT to FPUX86_HAS_AVXUNIT
+ mm register allocator can be initialized with 32 mm registers of AVX512

git-svn-id: trunk@42707 -
 2019-08-16 11:35:03 +00:00
pierre
d8b89432a2 * Set ControllerSupport to false for sparc/sparc64 and x86_64 CPUs. 
This boolean must only be set to true if TControllerType is not simply (ct_none)
  * ppu.pas: Increment CurrentPPULongVersion constant as the above modification
    changes the number of fields of the TSettings record that is saved to
    PPU in ST_LOADSETTINGS field.

git-svn-id: trunk@42323 -
 2019-07-04 15:24:49 +00:00
Jonas Maebe
eb742bcacc * pass on the value of -CfXXX to llc/clang for x86-64 
git-svn-id: branches/debug_eh@40438 -
 2018-12-01 20:30:46 +00:00
florian
31f78ea2b6 + implementation of the vectorcall calling convention by J. Gareth Moreton 
+ tests

git-svn-id: trunk@38206 -
 2018-02-11 17:50:37 +00:00
nickysn
aec03309ef + added CPUX86_HAS_SSE2 to x86 tcpuflags 
git-svn-id: trunk@37326 -
 2017-09-26 16:02:56 +00:00
florian
73c46a5988 - removed unused constants 
git-svn-id: trunk@35664 -
 2017-03-26 13:06:34 +00:00
Jonas Maebe
265c8e7bbc + support for specifying ms_abi_default, ms_abi_cdelc, sysv_abi_default, and 
sysv_abi_cdecl calling conventions on x86-64 to force using the SYSV/
    Microsoft ABI on platforms that don't use it by default (mainly to ease
    porting pure assembler routines)

git-svn-id: trunk@35425 -
 2017-02-11 19:57:12 +00:00
Jonas Maebe
2e9c6f35ae - disable -Ooregvar for the LLVM-based x86-64 code generator, as it causes 
internalerrors there and fixing it doesn't make sense since LLVM will take
    care of that anywaya

git-svn-id: trunk@35058 -
 2016-12-04 11:15:12 +00:00
Jeppe Johansen
3cb9be73bc Moved tcontrollerdatatype out into cpuinfo. 
Added cputype and fputype info to tcontrollerdatatype arrays.

git-svn-id: trunk@31574 -
 2015-09-07 20:36:54 +00:00
florian
de17e9fa1c + cpu capability CPUX86_HAS_CMOV 
git-svn-id: trunk@29776 -
 2015-02-21 20:47:40 +00:00
florian
5c67fcc43f + change always floating point divisions into multiplications if they are a power of two, 
this is an exact operation so it is always allowed
* change only divisions by normal numbers into multiplications

git-svn-id: trunk@29085 -
 2014-11-16 20:47:38 +00:00
Tomas Hajny
3ee3542744 * boolean constant instead of IFDEFs for detection of microcontroller support 
git-svn-id: trunk@29052 -
 2014-11-10 12:34:59 +00:00
florian
d88d644925 + support for FMA intrinsic: if there is no hardware support, the compiler throws an error. 
Currently it is implemented only for x86-CPUs supporting the FMA extension. While it would
  be possible to implement it in software or simulate fma(<single>,<single>,<single>) using
  double operations, it makes no sense in my opinion to do so.

git-svn-id: trunk@27564 -
 2014-04-13 19:21:54 +00:00
florian
0d6cc46a5e + CPU type corei 
git-svn-id: trunk@26790 -
 2014-02-16 08:27:27 +00:00
florian
d8c0f11ff9 + cs_userbp optimizer switch, so on x86-64 the compiler can make use of rbp if it is not needed as frame pointer 
git-svn-id: trunk@26633 -
 2014-01-30 19:44:17 +00:00
florian
060aa2a7fe + SSE and AVX unit cpu flags 
git-svn-id: trunk@26587 -
 2014-01-26 12:37:52 +00:00
florian
a752e3542d + more x86 cpu flags 
git-svn-id: trunk@26513 -
 2014-01-18 21:03:09 +00:00