- Removed TMIPSProcInfo.needs_frame_pointer, it duplicates pi_needs_stackframe flag.
- Don't save RA for leaf procedures.
* GP is caller-saved register, it does not need saving/restoring as nonvolatile registers. Handle its restore position as a "normal" temp, whose offset is known before secondpass. This allows to handle PIC calls without involving GAS macro processing.
git-svn-id: trunk@23885 -
+ Favor 'weak' parameter in a_call_name of both thlcgmips and TCGMIPS.
* make_simple_ref and a_loadaddr_ref_reg: require input references to be 'raw' (no refaddr=addr_pic, etc) and do not use GP as base/index. If it's not true, raise an internal error. When addr_pic_call16 or so needs to be generated, it must be done without calling the mentioned methods.
* thlcgmips.a_call_name: generate PIC sequence for procedures declared as 'external', instead of 'cdecl', this is more correct because ABI has only one calling convention.
- make_simple_ref_fpu removed, there's no reason to handle references to floating-point data in different way.
- a_loadaddr_ref_cgpara override also removed, generic method does the job just well.
- thlcgmips.a_call_ref and a_call_reg overrides removed because indirect calls are now always done using $t9.
git-svn-id: trunk@23698 -
* Abort if attempting to emit a call without pi_do_call flag set, because the outgoing parameter area determines layout of temps and therefore cannot be created/changed during pass 2.
* Bypass g_concatcopy_move if procedure is a leaf one, due to the restriction mentioned above.
git-svn-id: trunk@23644 -
* Parameters passed in registers are no longer forced to stack, therefore assembler routines using 'lw' instruction to load such parameters must have it changed to 'move' (tb0072.pp).
git-svn-id: trunk@23627 -
* Also changed parameter management to allocate a single LOC_REFERENCE location for any parameter (or part of a parameter) passed on stack. Such locations can now be handled by generic code. As a consequence, TGMIPS.a_load_const_cgpara and a_load_ref_cgpara methods are no longer necessary (moreover they were ignoring parameter shifting).
* a_loadfpu_ref_cgpara patched to handle 64-bit location, which are now possible.
* This change eliminates code generation madness where each word of a record was copied individually, thus passing by value a 32K-word sized record was bloating into 64K instructions, multiply this number by 2 for larger records due to limited immediate offsets, and by another 2 for global record in PIC mode :/
git-svn-id: trunk@23575 -
* cpugas.pas: GetReferenceString: rewritten, it is easier than trying to fix it. Fixes incorrect writing of non-PIC references containing base, symbol and offset together, and some forms of PIC references. Also supports newly introduced address types.
git-svn-id: trunk@23555 -
* Reused applicable code from the above mentioned method in tMIPSELnotnode.second_boolean, it is more efficient in handling 64-bit data.
git-svn-id: trunk@23531 -
- removed a_jmp_cond, it's not virtual and not applicable to this CPU.
* a_loadfpu_reg_cgpara: use direct register moves for simple destinations.
* g_concatcopy: don't take address of source/destination for small amounts of data if possible, for single 32-bit moves this reduces number of generated instructions from 4 to 2.
* g_intf_wrapper: 'Self' is in R4 (a0), not R2. Fixes test/tinterface1.pp.
* mips/cpupara.pas: for functions with result returned in parameter, pass its address in a0 only if result is a record. ABI does not specify behavior for types except records/unions. At the same time, Pascal code relies on the fact that results like strings/interfaces does not change their locations, i.e. "function foo(<self>): IInterface" can be invoked as "procedure foo(<self>, out obj)". This fixes test/tdel1.pp and some Variant-related tests.
git-svn-id: trunk@23377 -
ARM status: roughly corresponds to i386 one, passes the test suite. Handles libraries, can link static libc code including basic PIC and TLS IE/LE stuff. Completely misses Thumb support. Also does not handle ABI-specific stuff, for this reason internally linked .so cannot be used for linking executables with ld. Little-endian only. Tested only on "versatilepb" QEMU virtual machine.
MIPS status: can link the compiler and at least some dynamic executables including fpmake. Some PIC support is present but almost untested. Specific header flags and sections are also not handled yet. Written to handle both endian, but tested for big-endian only ("malta" QEMU VM), including cross-linking from x86_64.
git-svn-id: trunk@23376 -
that the type of the parameters can be determined automatically
o added compilerproc declarations for all helpers called in the compiler
via their assembler name, so we can look up the corresponding procdef
git-svn-id: trunk@23325 -
TRegNameTable is defined in compiler/rgbase.pas and is an array of
strings, limited to the maximum length of the used register names.
r22792 added a long register name but did not scale the string-size
enough, resulting in the compiler built breaking for arm.
git-svn-id: trunk@22817 -
fixes a couple of arm-embedded stuff,
adds some controllers, start of fpv4_s16 support, for a complete list of
changes see below:
------------------------------------------------------------------------
r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line
Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
------------------------------------------------------------------------
r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line
Fixed flags detections code for wide->short optimization code for Thumb-2
------------------------------------------------------------------------
r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
------------------------------------------------------------------------
r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line
Added register specifications to lpc1768.pp. From Joan Duran
------------------------------------------------------------------------
r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines
Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
------------------------------------------------------------------------
r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line
Added all STM32F1 configurations
------------------------------------------------------------------------
r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line
Added initial support for the Cortex-M4F FPv4_S16 FPU
------------------------------------------------------------------------
r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line
Added FPv4_d16 FPU instructions, and a few extra registers
------------------------------------------------------------------------
r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
------------------------------------------------------------------------
r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines
Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
------------------------------------------------------------------------
r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines
Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
------------------------------------------------------------------------
r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines
Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
------------------------------------------------------------------------
r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
------------------------------------------------------------------------
r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines
Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)
git-svn-id: trunk@22792 -
