florian
28c14ff345
+ RiscV: UMul64x64_128 assembler implementation
...
+ test
2025-03-15 23:10:48 +01:00
florian
27e17e3186
+ RiscV64: make use of rev8 instruction
2025-02-13 22:44:44 +01:00
florian
212b0fb7a8
* cleanup
2025-01-30 22:49:29 +01:00
florian
cd76562339
+ atomic operations for RV32
2025-01-26 14:17:39 +01:00
florian
f8c09568d8
* RiscV: unify stack related functions
2025-01-25 23:20:11 +01:00
florian
c6a68abfb6
* RiscV: unify memory barrier functions
2025-01-25 15:00:40 +01:00
florian
ca53c5e7d4
* unify SysInitFPU and SysResetFPU on RiscV
2025-01-25 14:43:10 +01:00
florian
9cac8e6183
+ add an SysInitFPU implementation
2025-01-23 23:00:30 +01:00
Sven/Sarah Barth
e94d02a067
* with all existing RTLs switched over to the atomic intrinsics, the define FPC_SYSTEM_INTERLOCKED_USE_INTRIN can be removed again
2024-12-12 22:05:20 +01:00
Sven/Sarah Barth
19d908a964
* switch RISC-V 64 RTL to provide atomic intrinsic helpers instead of Interlocked* functions
2024-12-12 22:05:18 +01:00
florian
db05be80bd
* typo
2024-08-20 23:07:53 +02:00
florian
a0cae50af6
* rtl part of #35433
2024-05-01 23:15:12 +02:00
Jonas Maebe
0758aa1143
FPU exception mask: generlised system unit interface
2022-10-17 19:43:01 +00:00
florian
90afbc8114
* RiscV: unified cpu initialization and FPU exception handling, resolves #38893
...
git-svn-id: trunk@49374 -
2021-05-15 20:53:56 +00:00
florian
d399df83ba
* RiscV32: fpc_longjmp needs nostackframe directive
...
* RiscV: unified procedure directives of fpc_*jmp
git-svn-id: trunk@48961 -
2021-03-14 13:34:30 +00:00
pierre
3362abb30c
* Set softfloat_rounding_mode indise SetRoundMode function for all CPUs.
...
* SetRoundMode returns previous rounding mode value for all CPUs.
git-svn-id: trunk@48018 -
2021-01-03 21:44:18 +00:00
Jeppe Johansen
e53cb61b11
Add support for softfloat in RISCV RTL.
...
git-svn-id: trunk@42334 -
2019-07-07 11:24:44 +00:00
florian
70b2e11e6a
* fix SetRoundingMode on RiscV64
...
git-svn-id: branches/laksen/riscv_new@39646 -
2018-08-19 15:26:44 +00:00
florian
4f052e4f90
o fix several issues with floating point exceptions
...
+ mask underflow and precision on startup
+ check for floating point exceptions after inlined float routine helpers
- do not check for floating point exceptions after floating point moves
git-svn-id: branches/laksen/riscv_new@39645 -
2018-08-19 15:26:00 +00:00
florian
203409ab48
* fixed floating point exception masking support for RiscV64
...
git-svn-id: branches/laksen/riscv_new@39638 -
2018-08-19 10:55:41 +00:00
Jeppe Johansen
f781c8942e
Write real atomic operations, and add memory barrier operations.
...
Add support for fence, and acquire/release syntax to assembler reader.
Fix broken register aliases.
git-svn-id: branches/laksen/riscv_new@39524 -
2018-07-29 16:43:09 +00:00
Jeppe Johansen
b98eb3daa9
Changed order in stack unravelling RTL code, to match the most common cases.
...
Fixed unsigned conditions for branch conditions.
Added some additional const loading cases.
Changed the temporary register used during calls because it could otherwise clash with the argument passing registers.
git-svn-id: branches/laksen/riscv_new@39492 -
2018-07-23 01:11:31 +00:00
Jeppe Johansen
dcb0f4fdb5
Fixed setjmp that overwrote a callee save register.
...
Disable relaxation for the gp load part of the prt0 code.
Fixed up some syscall definitions.
git-svn-id: branches/laksen/riscv_new@39478 -
2018-07-20 15:00:14 +00:00
Jeppe Johansen
6352328f3a
Update packages with information about RiscV.
...
Fix g_external_wrapper, since it uses a register.
Fixed calling of gas.
Ported cprt0.
git-svn-id: branches/laksen/riscv_new@39475 -
2018-07-20 10:40:28 +00:00
Jeppe Johansen
ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
...
git-svn-id: branches/laksen/riscv_new@39474 -
2018-07-20 08:21:15 +00:00
