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47 Commits

Author SHA1 Message Date
florian
9b18e39c81 * enable Lea2AddBase and Lea2AddIndex in TX86AsmOptimizer.PostPeepholeOptLea as we have flag tracking now 
* some flag allocations fixed

git-svn-id: trunk@38501 -
 2018-03-11 20:30:09 +00:00
florian
47927f053a * factored out TX86AsmOptimizer.OptPass1SHLSAL 
git-svn-id: trunk@38498 -
 2018-03-11 14:35:19 +00:00
florian
91514da267 * factored out TX86AsmOptimizer.PostPeepholeOptCall 
+ use TX86AsmOptimizer.PostPeepholeOptCall on x86-64

git-svn-id: trunk@38278 -
 2018-02-17 23:25:01 +00:00
florian
73fda1ccb6 * factored out OptPass1Sub 
+ make use of OptPass1Sub on x86_64 and i8086 as well

git-svn-id: trunk@37572 -
 2017-11-10 20:55:22 +00:00
florian
2140b586a6 * i386 building fixed 
git-svn-id: trunk@37554 -
 2017-11-04 19:42:08 +00:00
florian
4da4b768ec * factored out PostPeepholeOptTest 
+ use PostPeepholeOptTest on x86-64

git-svn-id: trunk@37551 -
 2017-11-04 19:10:14 +00:00
florian
3097eaf8ee * made PostPeepholeOptMov a function 
git-svn-id: trunk@37550 -
 2017-11-04 19:10:12 +00:00
florian
a7ea7fb569 * factored out PostPeepholeOptCmp 
+ use PostPeepholeOptCmp for x86_64

git-svn-id: trunk@37549 -
 2017-11-04 19:10:09 +00:00
nickysn
80226e3af4 + added an optimization pass, that optimizes x86 references 
git-svn-id: trunk@37494 -
 2017-10-20 15:55:55 +00:00
florian
15b617546e + call TX86AsmOptimizer.OptPass1VOP for logical operations as well 
git-svn-id: trunk@37367 -
 2017-10-01 14:40:21 +00:00
florian
05ecd784f2 * factored out OptPass1LEA and use it for x86-64 as well 
+ LEAMov2LEA optimization

git-svn-id: trunk@37199 -
 2017-09-13 20:40:32 +00:00
florian
22956c4393 + TX86AsmOptimizer.OptPass1OP 
git-svn-id: trunk@36365 -
 2017-05-28 13:49:43 +00:00
florian
0f16f6d94d + OptPass1MOVXX 
git-svn-id: trunk@36209 -
 2017-05-14 20:59:10 +00:00
florian
535c990233 + OptPass1MOVAP 
git-svn-id: trunk@36203 -
 2017-05-13 21:48:44 +00:00
florian
f4a29bb75d * moved InstructionLoadsFromReg and RegReadByInstruction from TCpuAsmOptimizer (i386) to TX86AsmOptimizer 
git-svn-id: trunk@36200 -
 2017-05-13 09:58:25 +00:00
florian
b1dff29cbf * removed unused units 
git-svn-id: trunk@36165 -
 2017-05-09 19:53:14 +00:00
florian
52d3756c26 * factored out OptPass1Movx and merged i386 and x86-64 version 
git-svn-id: trunk@36159 -
 2017-05-08 20:44:27 +00:00
florian
06c4c651fd * factored out PrePeepholeOptSxx 
+ x86-64 uses PrePeepholeOptSxx now as well

git-svn-id: trunk@36158 -
 2017-05-08 20:44:24 +00:00
florian
dd69ab5488 * cleanup after all old code from PeepHoleOptPass2 of i386 was moved to the common x86 optimizer class 
git-svn-id: trunk@36147 -
 2017-05-07 16:18:37 +00:00
florian
cd134ea5bb + DebugMsg 
git-svn-id: trunk@36146 -
 2017-05-07 16:18:35 +00:00
florian
7afe762d22 * factored out OptPass2Jcc assembler optimization 
* OptPass2Jcc now used by x86-64 as well
* remove orphaned alignments if the label is not used anymore after cmov is used

git-svn-id: trunk@36143 -
 2017-05-07 12:45:48 +00:00
florian
e3f0b338d4 * SkipLabels moved to aoptutils 
* factored out OptPass2Jmp assembler optimization
* OptPass2Jmp now used by x86-64 as well

git-svn-id: trunk@36141 -
 2017-05-06 21:07:02 +00:00
nickysn
0cd70844f1 + take into account the fact that lea doesn't read the segment register of its 
reference in i386's TCpuAsmOptimizer.RegReadByInstruction

git-svn-id: trunk@36080 -
 2017-05-04 14:13:53 +00:00
nickysn
d5d53e7017 * fixed operand order in the check for sse movsd in i386's 
TCpuAsmOptimizer.RegReadByInstruction

git-svn-id: trunk@36003 -
 2017-04-28 14:56:54 +00:00
nickysn
ff1ee6836d + fix RegReadByInstruction for the x86 MOVSD instruction 
git-svn-id: trunk@35968 -
 2017-04-27 14:42:08 +00:00
nickysn
b741e38f98 + precise handling for x86 conditions and their flag bits in i386's 
TCpuAsmOptimizer.RegReadByInstruction

git-svn-id: trunk@35965 -
 2017-04-27 12:07:48 +00:00
nickysn
0f010430cc + better precision in determining the registers, read by mul/imul/div/idiv in 
i386's TCpuAsmOptimizer.RegReadByInstruction:
  * mul doesn't read edx (unless included in operand)
  * 8-bit mul and imul don't read ah (unless included in operand)
  * 8-bit div and idiv don't read edx (unless included in operand)

git-svn-id: trunk@35958 -
 2017-04-26 16:17:31 +00:00
nickysn
916c09af55 + also check the register type when checking for specific integer registers in 
i386's TCpuAsmOptimizer.RegReadByInstruction. Previously, the lack of this
  check could generate false reads on some other register types (e.g. mmx/xmm/
  flags, etc.), and this could worsen optimizations.

git-svn-id: trunk@35957 -
 2017-04-26 15:25:38 +00:00
nickysn
618b6292ee + support testing for individual bits from the x86 flags register in i386's 
TCpuAsmOptimizer.RegReadByInstruction()

git-svn-id: trunk@35956 -
 2017-04-26 14:38:36 +00:00
nickysn
1d34e96064 + added x86 instruction flag Ch_RFLAGScc, indicating instructions that read 
specific bits from the flags register, according to their condition (used by
  Jcc/SETcc/CMOVcc)

git-svn-id: trunk@35907 -
 2017-04-22 22:07:05 +00:00
nickysn
1146b7c12c + added detailed information for individual flag bits use for most x86 
instructions. Not used by the compiler yet, but may allow more
  optimizations in the future.

git-svn-id: trunk@35882 -
 2017-04-21 23:03:33 +00:00
nickysn
869f395a31 + added knowledge to the compiler for the x86 instructions, that don't read 
their input registers, in case both parameters are the same register (e.g.
  xor eax, eax; sub eax, eax; etc.)

git-svn-id: trunk@35861 -
 2017-04-20 15:11:56 +00:00
nickysn
9303a8f61a * changed the x86 TInsProp.Ch structure from a 3-element array to a pascal set; 
this removes the limit of 3 Ch_XXX flags per instruction (thus allowing adding
  more precise flags, e.g. for tracking only certain bits of the flags register,
  etc.) and avoids the ugliness of having the Ch_None filler, which makes
  x86ins.dat less readable.

git-svn-id: trunk@35850 -
 2017-04-19 16:48:35 +00:00
florian
f68558b88c * factored out TX86AsmOptimizer.OptPass2Imul 
git-svn-id: trunk@35252 -
 2017-01-06 22:25:24 +00:00
Jonas Maebe
a25ebbba3e + added volatility information to all memory references 
o separate information for reading and writing, because e.g. in a
     try-block, only the writes to local variables and parameters are
     volatile (they have to be committed immediately in case the next
     instruction causes an exception)
   o for now, only references to absolute memory addresses are marked
     as volatile
   o the volatily information is (should be) properly maintained throughout
     all code generators for all archictures with this patch
   o no optimizers or other compiler infrastructure uses the volatility
     information yet
   o this functionality is not (yet) exposed at the language level, it
     is only for internal code generator use right now

git-svn-id: trunk@34996 -
 2016-11-27 18:17:37 +00:00
yury
649823a246 * Removed unused vars. 
git-svn-id: trunk@34405 -
 2016-09-01 20:01:54 +00:00
florian
7f44774852 * i386 uses OptPass1And from aoptx86 
git-svn-id: trunk@33936 -
 2016-06-07 20:01:13 +00:00
florian
5e8e21c1be * factored out OpPass2MOV code, x86-64 uses it as well now 
git-svn-id: trunk@33932 -
 2016-06-06 21:18:24 +00:00
florian
e56147ac6e * integrated mov op mov -> op optimization in aoptx86 
* isFoldableArithOp is in aoptx86 now

git-svn-id: trunk@33928 -
 2016-06-06 21:18:18 +00:00
florian
ba54f7243e * moved all i386 mov peephole optimization code into OptPass1MOV 
git-svn-id: trunk@33908 -
 2016-06-04 19:34:18 +00:00
florian
20807f4148 * factored out V<Op> optimizations into OptPass1VOP 
* call OptPass1VOP also for i386

git-svn-id: trunk@33878 -
 2016-06-01 20:49:35 +00:00
florian
bd54a11f1c + TX86AsmOptimizer.OptPass1VMOVAP for i386 and x86-64 
+ new unit aoptutils which helpers for the assembler optimizer

git-svn-id: trunk@33587 -
 2016-05-01 09:37:21 +00:00
florian
ec92bc3390 * case of identifiers fixed 
* x86-64 uses also the mov $0,... -> xor optimization

git-svn-id: trunk@33553 -
 2016-04-24 20:01:43 +00:00
florian
f0e75de730 * properly update allocation info of the involved register when carrying out an MovMovCmp2MovCmp optimization, resolves issue #30052 
* few changed to make code more readable

git-svn-id: trunk@33551 -
 2016-04-24 15:57:06 +00:00
florian
8d9f6bbe0b * disable some debugging code which does not work anymore due to the unification of the peephole optimizer 
git-svn-id: trunk@33546 -
 2016-04-22 20:31:25 +00:00
florian
77b4709e7a + i386 compiler tracks now flag usage if needed, so the mov $0,reg -> xor reg,reg transformation can be enabled 
git-svn-id: trunk@33545 -
 2016-04-22 19:44:26 +00:00
florian
3c2dab9878 * i386 peephole assembler uses largely the common peephole optimizer infrastructure, the resulting code is besides a few improvements the same 
git-svn-id: trunk@33542 -
 2016-04-21 20:14:01 +00:00