Commit Graph

20 Commits

Author SHA1 Message Date
nickysn
bf8d560cc6 * treat all Z80 registers as 8-bit
git-svn-id: branches/z80@44532 -
2020-04-03 18:53:10 +00:00
nickysn
5ddd0dd9b8 + implemented a_load_const_ref for more efficient Z80 code generation for const assignment to local variables
git-svn-id: branches/z80@44528 -
2020-04-03 02:23:05 +00:00
nickysn
4de1d5a8bf + Z80 stackframe generation
git-svn-id: branches/z80@44524 -
2020-04-03 00:15:24 +00:00
nickysn
20cd3a6d1b - removed GetLoad and GetStore from tcgz80. These came from AVR and I don't think they would be useful
for Z80.

git-svn-id: branches/z80@44512 -
2020-04-02 02:20:34 +00:00
nickysn
c02fc4a49f * fixed OP_NOT in tcgz80.a_op_reg_reg_internal
git-svn-id: branches/z80@44511 -
2020-04-02 02:14:21 +00:00
nickysn
052313d649 * fixed OP_AND,OP_OR,OP_XOR in tcgz80.a_op_reg_reg_internal
git-svn-id: branches/z80@44510 -
2020-04-02 02:04:18 +00:00
nickysn
cae1865f32 * fixes for OP_ADD and OP_SUB in a_op_reg_reg_internal. The destination of add/adc/sub/sbc can only be
register NR_A.

git-svn-id: branches/z80@44508 -
2020-04-02 01:10:52 +00:00
nickysn
d26b5199c8 + implemented a_load_ref_reg for fromsize=tosize for z80
git-svn-id: branches/z80@44507 -
2020-04-02 01:01:58 +00:00
nickysn
065a0d44d8 * tcg64favr renamed tcg64fz80
git-svn-id: branches/z80@44504 -
2020-04-01 23:32:02 +00:00
nickysn
fc80874e63 + implemented a_load_reg_reg for z80 for fromsize=tosize
git-svn-id: branches/z80@44502 -
2020-04-01 22:43:10 +00:00
nickysn
662ca13f51 * use register NR_A in a_load_reg_ref for z80
git-svn-id: branches/z80@44501 -
2020-04-01 22:40:02 +00:00
nickysn
fbadb3519f + implemented a_load_reg_ref for equal sized args for z80
git-svn-id: branches/z80@44498 -
2020-04-01 22:08:46 +00:00
nickysn
f87c837afe + implemented a_load_const_reg
git-svn-id: branches/z80@44489 -
2020-04-01 18:22:41 +00:00
nickysn
36a26a53ae + emit warning comments in the asm output for the unimplemented methods in cgcpu
git-svn-id: branches/z80@44487 -
2020-04-01 17:16:56 +00:00
nickysn
050244e5f0 + emit a ret instruction at the end of functions
git-svn-id: branches/z80@44485 -
2020-04-01 14:05:00 +00:00
nickysn
943d0cbbe2 * use the generic code of tcg.getintregister, which supports 8-bit CPUs after merging trunk
git-svn-id: branches/z80@44398 -
2020-03-29 17:04:49 +00:00
nickysn
755fe97c51 * synchronize with trunk
git-svn-id: branches/z80@44397 -
2020-03-29 16:24:32 +00:00
florian
9a4ff8daa4 * started to get some Z80 things working
git-svn-id: branches/z80@44284 -
2020-03-08 11:43:38 +00:00
florian
e370e9ba15 * register names fixed
git-svn-id: branches/z80@35670 -
2017-03-27 20:30:51 +00:00
florian
ea52a23179 + skeleton for Z80 support
git-svn-id: branches/z80@35665 -
2017-03-26 19:10:50 +00:00