first 16 registers in RISC-V RVE and RVEC modes. However, there was still
code in tcpuparamanager.create_paraloc_info_intern that allowed the allocation
of up to register X17 in RVE and RVEC modes. Modified this function to
take the processor mode into account and restrict it to X0..X15 in RVE and RVEC modes.
Also put conditional code in setjump.inc assembler code to only set the first
16 registers in RVE and RVEC modes.
The entire embedded-riscv32 RTL can now compile successfuly in RVEC mode.
Modified low-level startup code for RISCV32 embedded microcontrollers to
allow user code override of reset handlers for non-power-up reset events
as well as enabling user code override handlers for all 255 possible
interrupt vectors.
Separated out the low-level startup memory init into a callable procedure
to allow users that have caught reset events to init memory again if needed.
Signed-off-by: Interferon <brspm2@pinnaclesimulation.com>
that itself, our LLVM code generator can't handle it, and if it did then
afterwards we would have to spill 90% of those register variables again
to make them SSA)
git-svn-id: trunk@44062 -
- Clean up handling of CPU/FPU type handling in RISCV.
- Do more fixes to get RISCV32 working.
- Fix most soft multiplication handling for generic RISCV code. Still missing a few.
- Add RISCV embedded targets.
git-svn-id: trunk@42335 -
