florian 62236ec2bb * proper naming		2025-04-01 22:53:56 +02:00
..
aasmcpu.pas	* patch by Pierre to fix spilling and jump handling of pseudo-instructions	2025-03-31 22:53:40 +02:00
agrvgas.pas	+ RiscV: rv32gcb	2025-02-22 21:57:52 +01:00
aoptcpurv.pas	* proper naming	2025-04-01 22:53:56 +02:00
cgrv.pas	+ RiscV: ROL/ROR code generation support	2025-03-25 22:40:26 +01:00
cpubase.pas	* patch by Pierre to fix spilling and jump handling of pseudo-instructions	2025-03-31 22:53:40 +02:00
hlcgrv.pas
itcpugas.pas	+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0	2025-01-11 21:03:54 +01:00
nrvadd.pas	+ RiscV: support ZMMUL extension	2025-01-26 14:43:57 +01:00
nrvcnv.pas
nrvcon.pas	* RiscV: check for cpu capabilities before using fmv for loading zero	2025-01-12 18:30:32 +01:00
nrvinl.pas	+ min/max optimization support for RiscV	2025-01-06 15:21:18 +01:00
nrvmat.pas	+ RiscV: make use of the fneg.* instruction	2025-01-09 22:25:26 +01:00
nrvset.pas	+ RiscV64: apply OptPass1OP also to addiw	2024-11-13 22:56:13 +01:00
nrvutil.pas	* fix typo	2025-02-21 22:47:44 +01:00
pararv.pas	* RiscV: push_addr_param unified	2024-12-26 16:49:43 +01:00
rarv.pas	* unified RiscV32 and RiscV64 GAS readers	2021-03-07 08:53:03 +00:00
rarvgas.pas	* Risc-V: allow also register aliases in register modification lists after asm blocks, last part to resolve #39738	2022-06-03 22:54:18 +02:00
rgcpu.pas
rvreg.dat	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00