marco 5f8057775b --- Merging r30757 into '.': ... U compiler/generic/symcpu.pas U compiler/arm/symcpu.pas U compiler/symtable.pas U compiler/ia64/symcpu.pas U compiler/m68k/symcpu.pas U compiler/powerpc64/symcpu.pas U compiler/symconst.pas U compiler/mips/symcpu.pas U compiler/x86_64/symcpu.pas U compiler/i8086/symcpu.pas U compiler/powerpc/symcpu.pas U compiler/avr/symcpu.pas U compiler/symsym.pas U compiler/i386/symcpu.pas U compiler/alpha/symcpu.pas U compiler/jvm/symcpu.pas U compiler/sparc/symcpu.pas U compiler/pmodules.pas U compiler/aarch64/symcpu.pas U rtl/inc/text.inc --- Recording mergeinfo for merge of r30757 into '.': U . # revisions: 30757 ------------------------------------------------------------------------ r30757 | florian | 2015-05-01 22:58:31 +0200 (vr, 01 mei 2015) | 3 lines Changed paths: M /trunk/compiler/aarch64/symcpu.pas M /trunk/compiler/alpha/symcpu.pas M /trunk/compiler/arm/symcpu.pas M /trunk/compiler/avr/symcpu.pas M /trunk/compiler/generic/symcpu.pas M /trunk/compiler/i386/symcpu.pas M /trunk/compiler/i8086/symcpu.pas M /trunk/compiler/ia64/symcpu.pas M /trunk/compiler/jvm/symcpu.pas M /trunk/compiler/m68k/symcpu.pas M /trunk/compiler/mips/symcpu.pas M /trunk/compiler/pmodules.pas M /trunk/compiler/powerpc/symcpu.pas M /trunk/compiler/powerpc64/symcpu.pas M /trunk/compiler/sparc/symcpu.pas M /trunk/compiler/symconst.pas M /trunk/compiler/symsym.pas M /trunk/compiler/symtable.pas M /trunk/compiler/x86_64/symcpu.pas M /trunk/rtl/inc/text.inc o fixes handling of iso i/o parameters/program parameters: * explicit reset is needed * variable must be declared again ------------------------------------------------------------------------ git-svn-id: branches/fixes_3_0@33408 -		2016-04-02 14:47:24 +00:00
..
aasmcpu.pas	* MIPS: fixed O_MOVE_SOURCE and O_MOVE_DEST constants (they were swapped, amazing that it ever worked with such a mistake).	2014-09-03 19:57:46 +00:00
aoptcpu.pas	--- Merging r30110 into '.':	2015-12-14 12:53:53 +00:00
aoptcpub.pas
aoptcpud.pas
cgcpu.pas	* MIPS: improved code generation in make_simple_ref	2014-10-21 21:05:46 +00:00
cpubase.pas	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
cpuelf.pas	* ELF linker: track relocation style (REL or RELA) of each input section and use it instead of global default on MIPS targets. This fixes internal linking of tests/test/units/system/tres*.pp.	2014-11-13 22:10:53 +00:00
cpugas.pas	* Fixed condition to output div/divu having R0 as first operand as non-macros.	2014-12-29 23:19:01 +00:00
cpuinfo.pas	+ change always floating point divisions into multiplications if they are a power of two,	2014-11-16 20:47:38 +00:00
cpunode.pas	+ support overriding tdef/tsym methods with target-specific functionality:	2014-03-29 22:31:55 +00:00
cpupara.pas
cpupi.pas	* Moved fixup_jmps to target-specific classes for powerpc,powerpc64 and MIPS, cleaned out remaining $ifdef's. A slight functionality change is that fixup_jmps is now called before adding the procedure end symbol, not after, but that should not matter.	2014-04-02 14:17:23 +00:00
cputarg.pas	* partially merged the mips-embedded branch of Michael Ring:	2014-03-19 21:25:38 +00:00
hlcgcpu.pas	* partially merged the mips-embedded branch of Michael Ring:	2014-03-19 21:25:38 +00:00
itcpugas.pas
mipsreg.dat	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
ncpuadd.pas	+ MIPS: implement inline full 64-bit multiplication, for cases when overflow checking is off and CPU is set to mips32r2.	2014-12-28 22:03:15 +00:00
ncpucall.pas	* MIPS: clean up	2014-03-04 08:42:45 +00:00
ncpucnv.pas	--- Merging r30038 into '.':	2015-12-14 12:36:29 +00:00
ncpuinln.pas	* completed thlcgobj.location_force_fpureg(), use it everywhere and removed	2014-03-10 09:01:05 +00:00
ncpuld.pas
ncpumat.pas	+ Support (as target-independent as possible) optimization of division by constants:	2014-06-08 22:50:24 +00:00
ncpuset.pas	* MIPS and SPARC: determine whether case expression is in range using a single unsigned comparison (like it is done on other targets).	2014-03-10 23:02:05 +00:00
opcode.inc	+ MIPS: added movn and movz instructions.	2014-06-19 22:44:17 +00:00
racpugas.pas	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
rgcpu.pas	+ MIPS: support replacement spilling for mov.s, mov.d and (partially) mtc1 instructions.	2014-08-27 21:26:38 +00:00
rmipscon.inc	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
rmipsdwf.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgas.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgri.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgss.inc
rmipsnor.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsnum.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsrni.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssri.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssta.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsstd.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssup.inc	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
strinst.inc	+ MIPS: added movn and movz instructions.	2014-06-19 22:44:17 +00:00
symcpu.pas	--- Merging r30757 into '.':	2016-04-02 14:47:24 +00:00