..
aasmcpu.pas
* patch by Marģers to unify internal error numbers, resolves #37888
2020-10-13 19:59:01 +00:00
aoptcpu.pas
* Fixed the peephole optimization of conditional movs for mips.
2020-07-22 11:40:21 +00:00
aoptcpub.pas
- get rid of MaxOps, it is redundant with max_operands
2018-11-02 21:32:29 +00:00
aoptcpud.pas
cgcpu.pas
* patch by Marģers to unify internal error numbers, resolves #37888
2020-10-13 19:59:01 +00:00
cpubase.pas
* patch by J. Gareth Moreton, issue #36271 , part 3: support for the other architectures
2019-11-10 16:11:40 +00:00
cpuelf.pas
* patch by Marģers to unify internal error numbers, resolves #37888
2020-10-13 19:59:01 +00:00
cpugas.pas
* patch by Marģers to unify internal error numbers, resolves #37888
2020-10-13 19:59:01 +00:00
cpuinfo.pas
* disable cs_opt_regvar on all platforms when compiled for LLVM (LLVM does
2020-01-29 22:21:07 +00:00
cpunode.pas
* automatically generate necessary indirect symbols when a new assembler
2016-07-20 20:53:03 +00:00
cpupara.pas
* disable regular array -> dynamic array type coversion support unless
2019-05-25 12:31:32 +00:00
cpupi.pas
+ MIPS: take care of setnoat
2019-11-09 21:58:30 +00:00
cputarg.pas
* partially merged the mips-embedded branch of Michael Ring:
2014-03-19 21:25:38 +00:00
hlcgcpu.pas
* patch by Marģers to unify internal error numbers, resolves #37888
2020-10-13 19:59:01 +00:00
itcpugas.pas
* fix case completeness and unreachable code warnings in compiler that would
2019-05-12 14:29:03 +00:00
mipsreg.dat
Fix stabs number for FPU register, which start at 38 instead of 32
2016-11-06 18:01:08 +00:00
ncpuadd.pas
Fix for bug report 38549 about wrong code generation
2021-03-03 22:15:20 +00:00
ncpucall.pas
* use pocalls_cdecl and cstylearrayofconst more consistently instead of
2017-02-25 11:46:35 +00:00
ncpucnv.pas
* patch by Marģers to unify internal error numbers, resolves #37888
2020-10-13 19:59:01 +00:00
ncpuinln.pas
* patch by Marģers to unify internal error numbers, resolves #37888
2020-10-13 19:59:01 +00:00
ncpuld.pas
* fix case completeness and unreachable code warnings in compiler that would
2019-05-12 14:29:03 +00:00
ncpumat.pas
* reworked usage of tcgnotnode.handle_locjump
2020-08-05 21:15:32 +00:00
ncpuset.pas
* let all the case code generation work with tconstexprint instead of aint,
2019-02-24 19:58:37 +00:00
opcode.inc
+ MIPS: added movn and movz instructions.
2014-06-19 22:44:17 +00:00
racpugas.pas
* patch by Marģers to unify internal error numbers, resolves #37888
2020-10-13 19:59:01 +00:00
rgcpu.pas
* keep track of the temp position separately from the offset in references,
2018-04-22 17:03:16 +00:00
rmipscon.inc
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
2014-06-22 22:01:44 +00:00
rmipsdwf.inc
rmipsgas.inc
rmipsgri.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipsgss.inc
rmipsnor.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipsnum.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipsrni.inc
rmipssri.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipssta.inc
Regenerated after change in mipsreg.dat
2016-11-06 18:01:52 +00:00
rmipsstd.inc
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
2014-06-17 23:15:34 +00:00
rmipssup.inc
strinst.inc
+ MIPS: added movn and movz instructions.
2014-06-19 22:44:17 +00:00
symcpu.pas
tripletcpu.pas
* mark all external assemblers using an LLVM tool using af_llvm
2020-07-19 14:30:35 +00:00