sergei f85a8159ef * compiler/mips/cpuinfo.pas: removed "FPU_" prefixes from FPU names, not necessary because compiler inserts one itself. ... * rtl/embedded/system.pp: removed (commented out) FPU initialization from initialization of system unit, was dead code anyway because FPC_HAS_FEATURE_FPU is never defined and "feature FPU" does not exist. * rtl/mips/*.inc: don't compile FPU instructions if compiling RTL with -CfNONE or -CfSOFT (however, handling these switches for MIPS targets in compiler needs further fixing). git-svn-id: trunk@28670 -		2014-09-15 18:24:23 +00:00
..
aasmcpu.pas	* MIPS: fixed O_MOVE_SOURCE and O_MOVE_DEST constants (they were swapped, amazing that it ever worked with such a mistake).	2014-09-03 19:57:46 +00:00
aoptcpu.pas	* MIPS: doing progress with peephole optimizer.	2014-09-08 23:24:43 +00:00
aoptcpub.pas	* Patch from Fuxin Zhang: other mips and mipsel CPUs changes	2012-06-07 23:20:06 +00:00
aoptcpud.pas
cgcpu.pas	+ MIPS: make use of instructions MUL,SEB and SEH that are available in modern cores.	2014-09-03 19:59:00 +00:00
cpubase.pas	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
cpuelf.pas	* fixed DFA warnings for MIPS and AVR	2014-08-20 15:05:43 +00:00
cpugas.pas	* MIPS: dropped gas_std_regname, its functionality merged into std_regname. This fixes register names in non-instructions (reg. allocation information, variable locations, etc.) and makes assembler listings more readable.	2014-06-16 22:52:56 +00:00
cpuinfo.pas	* compiler/mips/cpuinfo.pas: removed "FPU_" prefixes from FPU names, not necessary because compiler inserts one itself.	2014-09-15 18:24:23 +00:00
cpunode.pas	+ support overriding tdef/tsym methods with target-specific functionality:	2014-03-29 22:31:55 +00:00
cpupara.pas	* MIPS: floating point parameters on stack should be loaded to/from FPU registers directly, without using temp.	2013-07-17 11:00:46 +00:00
cpupi.pas	* Moved fixup_jmps to target-specific classes for powerpc,powerpc64 and MIPS, cleaned out remaining $ifdef's. A slight functionality change is that fixup_jmps is now called before adding the procedure end symbol, not after, but that should not matter.	2014-04-02 14:17:23 +00:00
cputarg.pas	* partially merged the mips-embedded branch of Michael Ring:	2014-03-19 21:25:38 +00:00
hlcgcpu.pas	* partially merged the mips-embedded branch of Michael Ring:	2014-03-19 21:25:38 +00:00
itcpugas.pas
mipsreg.dat	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
ncpuadd.pas	+ MIPS: support floating point conditions in its emulated flags, on MIPS4+ convert such flags to registers using conditional move instructions (i.e. without branching). For older cores generated code remains the same.	2014-08-29 18:18:17 +00:00
ncpucall.pas	* MIPS: clean up	2014-03-04 08:42:45 +00:00
ncpucnv.pas	* MIPS: optimized conversion of unsigned 32-bit integers to float, now uses one integer register instead of two and does not generate redundant move.	2014-08-27 21:23:47 +00:00
ncpuinln.pas	* completed thlcgobj.location_force_fpureg(), use it everywhere and removed	2014-03-10 09:01:05 +00:00
ncpuld.pas	- Removed tcgloadnode.generate_picvaraccess, it is never used and is not necessary because PIC stuff is handled at lower levels.	2013-06-02 10:49:17 +00:00
ncpumat.pas	+ Support (as target-independent as possible) optimization of division by constants:	2014-06-08 22:50:24 +00:00
ncpuset.pas	* MIPS and SPARC: determine whether case expression is in range using a single unsigned comparison (like it is done on other targets).	2014-03-10 23:02:05 +00:00
opcode.inc	+ MIPS: added movn and movz instructions.	2014-06-19 22:44:17 +00:00
racpugas.pas	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
rgcpu.pas	+ MIPS: support replacement spilling for mov.s, mov.d and (partially) mtc1 instructions.	2014-08-27 21:26:38 +00:00
rmipscon.inc	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
rmipsdwf.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgas.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgri.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgss.inc
rmipsnor.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsnum.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsrni.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssri.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssta.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsstd.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssup.inc	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
strinst.inc	+ MIPS: added movn and movz instructions.	2014-06-19 22:44:17 +00:00
symcpu.pas	Fix a typo. The CPU specific version of "ttypesym" should be called "tcputypesym" and not "tcpuypesym".	2014-04-11 14:30:59 +00:00