fpc/compiler/arm
2012-10-22 21:12:29 +00:00
..
aasmcpu.pas Fix some optimizations which assume that there are 3 operands 2012-10-21 16:20:52 +00:00
agarmgas.pas - removed no longer used/supported af_allowdirect flag (direct assembler 2012-10-21 13:42:58 +00:00
aoptcpu.pas Disabled MulAdd2MLA and MulSub2MLS Peephole optimizers for thumb2 2012-10-22 15:30:24 +00:00
aoptcpub.pas * set MaxOps to 4 for the optimizer because fpc generates now mla instructions 2012-08-17 12:38:59 +00:00
aoptcpuc.pas
aoptcpud.pas
armatt.inc Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc) 2012-10-19 18:23:14 +00:00
armatts.inc Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc) 2012-10-19 18:23:14 +00:00
armins.dat Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc) 2012-10-19 18:23:14 +00:00
armnop.inc Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc) 2012-10-19 18:23:14 +00:00
armop.inc Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc) 2012-10-19 18:23:14 +00:00
armreg.dat + Cortex-M3 special registers, resolves #23185 2012-10-21 20:06:07 +00:00
armtab.inc Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc) 2012-10-19 18:23:14 +00:00
cgcpu.pas Fixed Bsf* functions on platforms that support RBIT 2012-10-21 19:13:59 +00:00
cpubase.pas Use TRegNameTable instead of array[tregisterindex] of string[10] 2012-10-22 10:23:21 +00:00
cpuinfo.pas Fixed Bsf* functions on platforms that support RBIT 2012-10-21 19:13:59 +00:00
cpunode.pas + take advantage of the mla instruction when calculating array offsets 2012-05-23 20:48:26 +00:00
cpupara.pas Added initial support for the Cortex-M4F FPv4_S16 FPU 2012-10-08 20:10:45 +00:00
cpupi.pas o merge of the branch laksen/arm-embedded of Jeppe Johansen: 2012-10-21 08:39:52 +00:00
cputarg.pas + some generic changes preparing for darwin/arm support 2008-10-02 15:10:13 +00:00
hlcgcpu.pas * create/destroy also the high level code generator for all architectures, 2011-08-20 07:21:16 +00:00
itcpugas.pas Use TRegNameTable instead of array[tregisterindex] of string[10] 2012-10-22 10:23:21 +00:00
narmadd.pas Added initial support for the Cortex-M4F FPv4_S16 FPU 2012-10-08 20:10:45 +00:00
narmcal.pas Added initial support for the Cortex-M4F FPv4_S16 FPU 2012-10-08 20:10:45 +00:00
narmcnv.pas Added initial support for the Cortex-M4F FPv4_S16 FPU 2012-10-08 20:10:45 +00:00
narmcon.pas * fixed ARM and MIPS compilation after r14912 2010-02-18 21:19:17 +00:00
narminl.pas Added initial support for the Cortex-M4F FPv4_S16 FPU 2012-10-08 20:10:45 +00:00
narmmat.pas Added initial support for the Cortex-M4F FPv4_S16 FPU 2012-10-08 20:10:45 +00:00
narmmem.pas + take advantage of the mla instruction when calculating array offsets 2012-05-23 20:48:26 +00:00
narmset.pas + a lot missing flag allocs/deallocs added 2012-08-23 08:54:52 +00:00
pp.lpi.template * improved template with help from Mattias Gaertner 2006-08-28 20:29:04 +00:00
raarm.pas o patch by Jeppe Johansen to fix mantis #17472: 2010-12-24 15:54:39 +00:00
raarmgas.pas Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc) 2012-10-19 18:23:14 +00:00
rarmcon.inc + Cortex-M3 special registers, resolves #23185 2012-10-21 20:06:07 +00:00
rarmdwa.inc + Cortex-M3 special registers, resolves #23185 2012-10-21 20:06:07 +00:00
rarmnor.inc + Cortex-M3 special registers, resolves #23185 2012-10-21 20:06:07 +00:00
rarmnum.inc + Cortex-M3 special registers, resolves #23185 2012-10-21 20:06:07 +00:00
rarmrni.inc + Cortex-M3 special registers, resolves #23185 2012-10-21 20:06:07 +00:00
rarmsri.inc + Cortex-M3 special registers, resolves #23185 2012-10-21 20:06:07 +00:00
rarmsta.inc + Cortex-M3 special registers, resolves #23185 2012-10-21 20:06:07 +00:00
rarmstd.inc + Cortex-M3 special registers, resolves #23185 2012-10-21 20:06:07 +00:00
rarmsup.inc + Cortex-M3 special registers, resolves #23185 2012-10-21 20:06:07 +00:00
rgcpu.pas Added support for IT block merging 2012-10-08 14:07:40 +00:00