TRegNameTable is defined in compiler/rgbase.pas and is an array of
strings, limited to the maximum length of the used register names.
r22792 added a long register name but did not scale the string-size
enough, resulting in the compiler built breaking for arm.
git-svn-id: trunk@22817 -
Add simple Mul+Sub/Mul+Add into MLS/MLA optimizations
Fix some other small issues in the optimizer
Implement Interlocked* functions with proper use of LDREX/STREX
git-svn-id: branches/laksen/arm-embedded@22801 -
fixes a couple of arm-embedded stuff,
adds some controllers, start of fpv4_s16 support, for a complete list of
changes see below:
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r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line
Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
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r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line
Fixed flags detections code for wide->short optimization code for Thumb-2
------------------------------------------------------------------------
r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
------------------------------------------------------------------------
r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line
Added register specifications to lpc1768.pp. From Joan Duran
------------------------------------------------------------------------
r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines
Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
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r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line
Added all STM32F1 configurations
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r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line
Added initial support for the Cortex-M4F FPv4_S16 FPU
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r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line
Added FPv4_d16 FPU instructions, and a few extra registers
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r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
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r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines
Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
------------------------------------------------------------------------
r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines
Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
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r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines
Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
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r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
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r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines
Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)
git-svn-id: trunk@22792 -
The function regLoadedWithNewValue returned true if the oper[0].reg
matched in an STR instruction, which is wrong as it will only be read.
git-svn-id: trunk@22623 -
Up until now DataMov2Data could be run on an strb generated by
AndStrb2Strb.
Code like this:
and reg0, reg1, #255
strb reg0, [r13]
mov reg2,reg1
would get transformed into:
strb reg2, [r13]
which is clearly wrong. The problem was that DataMov2Data expected that
it's first parameter is an instruction which loads new data into
oper[0]. With the introduction of AndStrb2Strb this wasn't true anymore.
This fix now checks if the first register is actually written to, this
is done by using regLoadedWithNewValue.
git-svn-id: trunk@22622 -
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
git-svn-id: branches/laksen/arm-embedded@22590 -
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
git-svn-id: branches/laksen/arm-embedded@22582 -
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
git-svn-id: branches/laksen/arm-embedded@22581 -
and add usermode parsing of LDM/STM ops
This patch basically extends the ARM assembly reader a bit to properly parse CPSR and
SPSR flags for the MSR opcode, and allows the reader to understand
the ^ modifer for register lists for STMxx and LDMxx.
Previously the following combinations weren't possible in straight assembler:
MRS R0, CPSR
MRS R0, SPSR
MSR CPSR_CX, R0
LDMIA SP, {R0-R15}^
etc..
git-svn-id: trunk@22502 -
We don't need to check for the postfix, PF_NONE/PF_H/PF_B are all ok for us and
can be intermixed. This allows the peephole optimizer to work for
strb and strh instructions.
git-svn-id: trunk@22367 -
tarmaddnode.second_cmpsmallset always forced a value into a register
even when it could be represented as a constant, resulting in wasted
registers.
mov r1, #5
cmp r0, r1
If possible we'll now create:
cmp r0, #5
git-svn-id: trunk@22366 -
It is the same as the normal MatchInstruction function but supports to
be called with a set of TAsmOps instead of a single op.
git-svn-id: trunk@22231 -
