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113 Commits

Author SHA1 Message Date
Karoly Balogh
c577ac5ce9 m68k: add tables to convert from some stub opcodes + condition into real opcodes. Use them in the external assembler writer for now. Later the internal assembler will need these tables too. 2023-01-30 09:56:41 +01:00
Karoly Balogh
69761839c0 m68k: removed the unused S_IQ opsize 2023-01-09 12:01:10 +01:00
Karoly Balogh
459dc68ab9 m68k: more boiler plate and refactor for a future internal assembler 2023-01-05 13:32:34 +01:00
Karoly Balogh
f2d6b4d530 m68k: added a helper function to check if a register is an FPU register 2023-01-05 13:32:33 +01:00
Károly Balogh
2a7aa11163 m68k: added support to references like (a0,d0.w) in inline assembly, also fixed a bug, where sometimes the index register would have been randomly set as smaller than .l size, when the size wasn't specified 
git-svn-id: trunk@49233 -
 2021-04-19 09:13:02 +00:00
florian
a0a8a6911a * m68k: proper values for first_*_reg 
git-svn-id: trunk@47761 -
 2020-12-11 22:14:16 +00:00
florian
a849e51a3c + m68k: JSR, RTS to JMP optimization 
git-svn-id: trunk@47740 -
 2020-12-09 20:57:06 +00:00
Károly Balogh
6753f86987 m68k: migrate the compiler to the new instruction tables and drop the old ones 
git-svn-id: trunk@45312 -
 2020-05-08 12:33:04 +00:00
florian
b7c6e01b03 * cleaning up tcgsize: it makes no sense to declare every combination and type 
the different vector types must be either handled in the high level cg or
    by using the shuffle parameter

git-svn-id: trunk@43860 -
 2020-01-04 21:54:53 +00:00
florian
e1e8986462 * patch by J. Gareth Moreton, issue #36271, part 3: support for the other architectures 
git-svn-id: trunk@43441 -
 2019-11-10 16:11:40 +00:00
Károly Balogh
eb71d11b99 m68k: also handle OS_64 register sizes in cgsize2subreg 
git-svn-id: trunk@43045 -
 2019-09-20 13:48:30 +00:00
Károly Balogh
19a6964088 m68k: add subregisters. on 68k, these are not as universal as on x86 and work differently, but the compiler needs this infrastructure to do 16bit math (which is a massive improvement on '000) or word-size indexes on CPUs which support it 
git-svn-id: trunk@43043 -
 2019-09-20 11:35:35 +00:00
Károly Balogh
353fc13257 m68k: cleanup of the ancient mess from cgsize2subreg 
git-svn-id: trunk@42949 -
 2019-09-08 13:55:19 +00:00
Károly Balogh
16fc8c8d9a m68k: added some handling for the explicit precision FPU instructions in the spilling and optimizer. fixed a_fsabs and a_fdabs names 
git-svn-id: trunk@42943 -
 2019-09-08 09:21:17 +00:00
Károly Balogh
db2875ceba m68k: added the remaining instructions with explicit rounding precision. fixed fsflmul to be fsglmul (this is also typo in the original 68k PRM) 
git-svn-id: trunk@42928 -
 2019-09-06 07:25:45 +00:00
Károly Balogh
2a87b885b1 m68k: added the most important FPU instructions with explicit rounding precision (eg. FSADD/FDADD) 
git-svn-id: trunk@42927 -
 2019-09-05 21:51:36 +00:00
Károly Balogh
5eee29e5d1 m68k: refactor some code to not fail when the tasmop set will be bigger than 256 elements 
git-svn-id: trunk@42926 -
 2019-09-05 21:49:27 +00:00
florian
69786ffe73 somehow committing went wrong, second part of last commit: 
+ AArch64: support for vX.8b/vX.16b register names
+ support for more than 256 registers in the register dat files
- removed totherregisterset
+ AArch64: use vmov to load immediates if possible
+ AArch64: use eor to clear mm registers

git-svn-id: trunk@42917 -
 2019-09-03 21:07:33 +00:00
Jonas Maebe
8555ec1438 + fpc_eh_return_data_regno() intrinsic to get the return register numbers 
for the Dwarf EH exception handler result

git-svn-id: branches/debug_eh@40070 -
 2018-10-28 18:16:38 +00:00
pierre
92acd38f40 Fix for bug report #34380 
git-svn-id: trunk@39986 -
 2018-10-18 20:21:54 +00:00
nickysn
518cdf9674 * replaced the saved_XXX_registers arrays with virtual methods inside 
tcpuparamanager, very similar to the existing get_volatile_registers_XXX. The
  new methods are called get_saved_registers_XXX, where XXX is the register
  type ("int", "address", "fpu" or "mm")

git-svn-id: trunk@38794 -
 2018-04-19 21:22:16 +00:00
Károly Balogh
66d180187a m68k: fix build after r38206 
git-svn-id: trunk@38210 -
 2018-02-11 18:20:51 +00:00
Károly Balogh
58d98d8cd7 m68k: made the PIC_OFFSET_REGs runtime changeable, and applied some defaults 
git-svn-id: trunk@37895 -
 2018-01-04 07:50:50 +00:00
Károly Balogh
41f72a0e6d m68k: some initial support for C ABIs which use an address register to return structs by address 
git-svn-id: trunk@36592 -
 2017-06-24 19:03:58 +00:00
Károly Balogh
b481129f4e m68k: for cdecls with the SVR4 ABI return results both in A0 and D0 
git-svn-id: trunk@36588 -
 2017-06-23 19:21:20 +00:00
Jonas Maebe
880d438704 * renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can 
inherit from it for LLVM without a thousand ifdefs

git-svn-id: trunk@35141 -
 2016-12-16 22:41:21 +00:00
Károly Balogh
c4e954c9a5 m68k: added fint and fintrz instructions 
git-svn-id: trunk@34991 -
 2016-11-27 17:42:24 +00:00
Károly Balogh
a2a630e9c5 m68k: fixed and enabled hardware mod/div support for coldfire, also it no longer depends on cpu family but cpu capability 
git-svn-id: trunk@33821 -
 2016-05-26 16:54:39 +00:00
Károly Balogh
b6d845e732 m68k: needs_unaligned helper. returns true when the given reference with the given size needs to be loaded with unaligned support on the given cpu 
git-svn-id: trunk@33806 -
 2016-05-25 23:56:24 +00:00
Károly Balogh
50a40062e2 m68k: fixed the build after r33614 
git-svn-id: trunk@33617 -
 2016-05-02 15:01:47 +00:00
Károly Balogh
92b2cf917d m68k: when saving/restoring FPU registers, use the right FPU register size on ColdFire to calculate the stored size 
git-svn-id: trunk@33614 -
 2016-05-02 14:18:30 +00:00
Károly Balogh
23106882ac m68k: extended TResFlags with float resflags 
git-svn-id: trunk@33557 -
 2016-04-25 23:30:56 +00:00
Károly Balogh
bd564b8933 m68k: some code to support the ColdFire v4e FPU. not functional yet. 
git-svn-id: trunk@33533 -
 2016-04-18 03:25:32 +00:00
Károly Balogh
288fa53694 m68k: is_calljmp cleanup 
git-svn-id: trunk@32848 -
 2016-01-05 04:07:00 +00:00
Károly Balogh
9c12615f09 m68k: new isregoverlap function, which returns true if the two registers overlap (same type and subreg). use the new r68kbss.inc for regnumber_count_bsstart. other minor tweaks. 
git-svn-id: trunk@32655 -
 2015-12-13 17:48:47 +00:00
Károly Balogh
258b42de26 m68k: added support for FSIN/FCOS. these are software supported on the 68040, so we should have a separate 68040/060 FPU option too, to avoid these in the future. 
git-svn-id: trunk@30257 -
 2015-03-17 22:52:53 +00:00
Károly Balogh
c062e55aa2 m68k: after a compare on the FPU, move the condition flags back to the CPU. this should make floating point compare actually working 
git-svn-id: trunk@29704 -
 2015-02-15 13:41:40 +00:00
Károly Balogh
9d6f763d4f m68k: small helpers to determine a given int value fits into a certain size or instruction argument 
git-svn-id: trunk@29605 -
 2015-02-02 08:25:01 +00:00
Károly Balogh
6070ac3def m68k: some more basic FPU stuff 
git-svn-id: trunk@29407 -
 2015-01-05 05:26:44 +00:00
Károly Balogh
8acc260a09 m68k: added the byterev and ff1 CF ISAA+/ISAC instructions, also added byterev as a CPU capability 
git-svn-id: trunk@28679 -
 2014-09-16 01:39:02 +00:00
sergei
c79cd3beca * m68k: fixed/completed the inverse_cond function. 
git-svn-id: trunk@28052 -
 2014-06-25 05:23:30 +00:00
Károly Balogh
7ee09b9620 instead of supporting SP only, have register A7 defined, and have SP as an alias 
git-svn-id: trunk@27572 -
 2014-04-13 21:02:16 +00:00
Károly Balogh
80b253c111 be consistent in naming. renamed VOLATILE_ADDRESSREGISTER to VOLATILE_ADDRESSREGISTERS 
git-svn-id: trunk@26463 -
 2014-01-15 01:31:41 +00:00
Károly Balogh
97864d7cbd trying harder to commit compilable code (manual merge fail) 
git-svn-id: trunk@25764 -
 2013-10-13 18:31:43 +00:00
Károly Balogh
3b99974847 set up register A6 to be saved as well. this will only happen in case A6 is not used as framepointer 
git-svn-id: trunk@25759 -
 2013-10-13 16:12:32 +00:00
Károly Balogh
dfe2f253f9 added 68040 CPU type, MOVE16 and ColdFire V4 extra instructions 
git-svn-id: trunk@25742 -
 2013-10-10 22:01:58 +00:00
Károly Balogh
280ee919b7 removed several debug writeln()s 
git-svn-id: trunk@25741 -
 2013-10-10 21:20:20 +00:00
svenbarth
c48d572996 Implement support for saving and restoring address registers. 
cgobj.pas, tcg:
  * g_save_registers: add the amount of used address registers to size as well
  * g_save_registers: save all used address registers
  * g_restore_registers: restore all stored address registers
m68k/cpubase.pas:
  * rename saved_standard_address_registers to saved_address_registers
all other platform's cpubase.{inc,pas} (except alpha, ia64 and vis which are not up to date):
  * add a saved_address_registers variable with one entry of RS_INVALID

At least a "make fullcycle" did complete.

git-svn-id: trunk@25664 -
 2013-10-05 21:43:42 +00:00
Károly Balogh
55be015a4e better version of the ColdFire TST.L 123(dX) fix, fixes regressions in tcnvint1 and 2 
git-svn-id: trunk@25651 -
 2013-10-05 16:52:39 +00:00
svenbarth
03623c6c1a Forgot to commit that I moved tcgsize2opsize from cgcpu to cpubase. 
git-svn-id: trunk@25630 -
 2013-10-03 14:34:54 +00:00