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3d81c8e51d
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419 Commits

Author SHA1 Message Date
florian
3d81c8e51d * re-activate copy_mm: using it instead of movs might reduce register pressure 
git-svn-id: trunk@45482 -
 2020-05-24 13:56:41 +00:00
florian
8f0a3cfce7 * x86-64: adjust stack by push/pop if possible 
git-svn-id: trunk@45476 -
 2020-05-23 17:50:13 +00:00
florian
7dbab3a78f * handle OP_XOR for a full mm register correctly in tcgx86.opmm_loc_reg 
git-svn-id: trunk@45348 -
 2020-05-12 20:43:15 +00:00
nickysn
0f6ab0de17 * handle LOC_(C)SUBSETREG/REF in second_NegNot_assign 
* changed the way OP_NEG and OP_NOT are handled in op_reg_ref, in order to be
  consistent with op_reg_reg
* introduced op_reg,op_ref,op_subsetreg,op_subsetref and op_loc for the unary
  operations only (OP_NEG,OP_NOT)

git-svn-id: trunk@45302 -
 2020-05-07 02:43:02 +00:00
florian
70a836c4a2 * first part of merging parts of Jeppe's intrinsics patch, mainly r31135 
is merged by this commit with a lot of adaptions

git-svn-id: trunk@43949 -
 2020-01-14 21:52:39 +00:00
florian
a34ae2261a * copy fpu parameters using fld/fst onto the stack 
git-svn-id: trunk@43861 -
 2020-01-04 22:19:15 +00:00
florian
b7c6e01b03 * cleaning up tcgsize: it makes no sense to declare every combination and type 
the different vector types must be either handled in the high level cg or
    by using the shuffle parameter

git-svn-id: trunk@43860 -
 2020-01-04 21:54:53 +00:00
florian
7000d82dcd * do not convert cmp 0,... into test ...,... before the post pass of the peephole optimizer 
as this conversion might result in missing further optimizer opportunities

git-svn-id: trunk@43596 -
 2019-11-26 22:09:34 +00:00
florian
a7e72617a6 * fix stackmisalignment calculation to take care of pushf/push cs, before r43503, 
it was correct by coincidence

git-svn-id: trunk@43506 -
 2019-11-17 09:14:54 +00:00
florian
240acc10f8 * fix calculation of stackmisalignment for interrupt procedures as pointed out by Jonas 
git-svn-id: trunk@43503 -
 2019-11-16 17:46:39 +00:00
florian
896e031e84 * interrupt procedures fixed for i386 targets with a fixed stack with 16 byte alignment 
git-svn-id: trunk@43006 -
 2019-09-15 17:17:27 +00:00
florian
ba203c0564 + x86 makes use of fpu_capabilities 
* moved CPUX86_HAS_AVXUNIT to FPUX86_HAS_AVXUNIT
+ mm register allocator can be initialized with 32 mm registers of AVX512

git-svn-id: trunk@42707 -
 2019-08-16 11:35:03 +00:00
Jonas Maebe
1b6425176b * synchronised with trunk till r42049 
git-svn-id: branches/debug_eh@42050 -
 2019-05-12 18:44:05 +00:00
Jonas Maebe
281b3ad276 * fix case completeness and unreachable code warnings in compiler that would 
be introduced by the next commit

git-svn-id: trunk@42046 -
 2019-05-12 14:29:03 +00:00
Jonas Maebe
a7bd37d17a * synchronised with trunk till r40776 
git-svn-id: branches/debug_eh@41867 -
 2019-04-13 15:16:09 +00:00
nickysn
8f8aa70074 + OpenBSD i386 and x86_64 support in tcgx86.g_profilecode 
git-svn-id: trunk@41760 -
 2019-03-21 17:09:21 +00:00
Jonas Maebe
866331de34 * fixed CFI registers for leave on x86-64, and place CFI directives closer to 
the instructions they apply to

git-svn-id: branches/debug_eh@41576 -
 2019-03-03 17:14:56 +00:00
florian
367bc18bc5 * cfa for x86-64 fixed 
git-svn-id: branches/debug_eh@41563 -
 2019-03-02 23:03:32 +00:00
Jonas Maebe
50c82b6468 * synchronised with trunk till r41537 
git-svn-id: branches/debug_eh@41538 -
 2019-03-01 16:20:22 +00:00
yury
a04e4971fc * i386: Do not request GOT for every function call. GOT is requested only for external calls in thlcgcpu.a_call_name(). Local calls are always PC relative. 
git-svn-id: trunk@41464 -
 2019-02-25 15:48:41 +00:00
florian
db6916453d * warning fixed 
git-svn-id: branches/debug_eh@41452 -
 2019-02-24 20:03:23 +00:00
florian
18fb53e012 * set cfa offset always properly 
git-svn-id: branches/debug_eh@41413 -
 2019-02-22 22:00:20 +00:00
florian
a8c8cc1890 * create proper cfi, when registers are pushed 
git-svn-id: branches/debug_eh@41382 -
 2019-02-19 22:16:39 +00:00
florian
3567d01ee4 * improved CFI 
git-svn-id: branches/debug_eh@41356 -
 2019-02-17 20:26:32 +00:00
florian
72a02b467c + generate more cfi on x86 
git-svn-id: branches/debug_eh@41287 -
 2019-02-10 18:00:24 +00:00
florian
597a23d278 + tls support for x86_64-linux (not yet enabled by default) 
git-svn-id: trunk@41081 -
 2019-01-27 09:37:25 +00:00
florian
6dbde11f5a * three operand shl for shifting by 2, 4 or 8 can be simulated by lea 
git-svn-id: trunk@40337 -
 2018-11-17 15:08:22 +00:00
florian
6a6ea6729f * i8086 compiler fixed, resolves #34552 
git-svn-id: trunk@40316 -
 2018-11-14 18:05:35 +00:00
florian
e157939b41 * compilation on x86-64 and i8086 fixed 
git-svn-id: trunk@40275 -
 2018-11-08 18:45:16 +00:00
florian
063415fa72 + i386-linux support for tls-based threadvars 
git-svn-id: trunk@40272 -
 2018-11-07 22:03:02 +00:00
pierre
c6977a0a7a Explicitly disable range checking 
git-svn-id: trunk@40026 -
 2018-10-24 21:37:22 +00:00
Jonas Maebe
0b246f3dbd * converted Boolean8 to an internal type, and mapped Boolean to the 
new internal pasbool1(type) (part of mantis #34411)
   o apply the _Bool x86-64 parameter passing rules only to pasbool1

git-svn-id: trunk@39949 -
 2018-10-16 21:14:18 +00:00
Jonas Maebe
4686f61002 * keep track of the temp position separately from the offset in references, 
so that they can still be freed after the reference has been changed
    (e.g. in case of array indexing or record field accesses) (mantis #33628)

git-svn-id: trunk@38814 -
 2018-04-22 17:03:16 +00:00
nickysn
518cdf9674 * replaced the saved_XXX_registers arrays with virtual methods inside 
tcpuparamanager, very similar to the existing get_volatile_registers_XXX. The
  new methods are called get_saved_registers_XXX, where XXX is the register
  type ("int", "address", "fpu" or "mm")

git-svn-id: trunk@38794 -
 2018-04-19 21:22:16 +00:00
florian
9b18e39c81 * enable Lea2AddBase and Lea2AddIndex in TX86AsmOptimizer.PostPeepholeOptLea as we have flag tracking now 
* some flag allocations fixed

git-svn-id: trunk@38501 -
 2018-03-11 20:30:09 +00:00
florian
381cf78ff1 * there is no vmovq for mmx registers 
git-svn-id: trunk@38208 -
 2018-02-11 17:50:41 +00:00
florian
31f78ea2b6 + implementation of the vectorcall calling convention by J. Gareth Moreton 
+ tests

git-svn-id: trunk@38206 -
 2018-02-11 17:50:37 +00:00
florian
092223f400 * comment links to test now 
git-svn-id: trunk@38204 -
 2018-02-11 16:38:33 +00:00
florian
e5ebc65cce * if si and di are allocated on i8086, using an index in references is not possible anymore 
git-svn-id: trunk@38203 -
 2018-02-11 15:54:37 +00:00
nickysn
b3f7bce3a6 * check for CPUX86_HAS_SSE2 instead of CPUX86_HAS_SSEUNIT in Tcgx86.g_concatcopy 
git-svn-id: trunk@37327 -
 2017-09-26 16:05:23 +00:00
florian
dba1761a76 + tcgx86.a_load_reg_ref cuts data if the ref. size is smaller than the reg. size 
git-svn-id: trunk@36953 -
 2017-08-20 16:45:02 +00:00
nickysn
7b70848d83 + allow the src register size to be different from the op size or the dst 
register size for OP_SHR/OP_SHL/OP_SAR/OP_ROL/OP_ROR in tcgx86.a_op_reg_reg().
  This is required for the in_[shr/shl/sar/rol/ror]_assign_x_y inline nodes.

git-svn-id: trunk@36251 -
 2017-05-19 14:03:13 +00:00
florian
b1dff29cbf * removed unused units 
git-svn-id: trunk@36165 -
 2017-05-09 19:53:14 +00:00
florian
5c2c5d72a2 * use avx for copying data only on i386 for 8 byte chunks 
git-svn-id: trunk@36149 -
 2017-05-07 16:18:42 +00:00
nickysn
ec11864272 * use a native sized int register for the shift count in in_sar_assign_x_y, 
in_shl_assign_x_y,in_shr_assign_x_y,in_rol_assign_x_y,in_ror_assign_x_y

git-svn-id: trunk@35857 -
 2017-04-20 12:38:54 +00:00
nickysn
16af6f03fb + support OP_SHR/OP_SHL/OP_SAR/OP_ROL/OP_ROR in tcgx86.a_op_reg_ref 
git-svn-id: trunk@35837 -
 2017-04-18 15:14:28 +00:00
nickysn
256dc546ac + implemented the in_neg_assign_x and in_not_assign_x inline nodes, which will 
be used (TBD in a future commit) for optimizing x:=-x and x:=not x on CPUs
  that support performing these operations directly in memory (such as x86)

git-svn-id: trunk@35749 -
 2017-04-07 16:02:40 +00:00
florian
1e374df5b8 * correctly calculate the bit mask in thlcgobj.a_load_regconst_subsetreg_intern, resolves #31042 
* convert immediates on x86 always to 32 (x86-64, i386) or 16 bit (i8086) signed values

git-svn-id: trunk@35082 -
 2016-12-07 20:08:22 +00:00
Jonas Maebe
a25ebbba3e + added volatility information to all memory references 
o separate information for reading and writing, because e.g. in a
     try-block, only the writes to local variables and parameters are
     volatile (they have to be committed immediately in case the next
     instruction causes an exception)
   o for now, only references to absolute memory addresses are marked
     as volatile
   o the volatily information is (should be) properly maintained throughout
     all code generators for all archictures with this patch
   o no optimizers or other compiler infrastructure uses the volatility
     information yet
   o this functionality is not (yet) exposed at the language level, it
     is only for internal code generator use right now

git-svn-id: trunk@34996 -
 2016-11-27 18:17:37 +00:00
svenbarth
c8202061dc * get rid of addr_load_indirect again by having tcgx86 provide an internal implementation of both make_simple_ref() and a_load_ref_reg() so that make_direct_ref() can call the latter (and the latter the former) without fear of inifinite recursive calls due to the symbol; a_load_ref_reg() is additionally declared as "final" as a_load_ref_reg_internal() needs to be overloaded instead (which is the case for tcg8086) 
git-svn-id: trunk@34579 -
 2016-09-30 14:01:02 +00:00