Commit Graph

278 Commits

Author SHA1 Message Date
tg74
4265f4d6a5 avx512 broadcast for special opcodes vfpclass.., vcvt...
git-svn-id: branches/tg74/avx512@39768 -
2018-09-19 06:25:42 +00:00
tg74
3759eac608 bugfix avx512 add ZMMReg for gather/scatter in intelOS32
git-svn-id: branches/tg74/avx512@39741 -
2018-09-12 06:11:44 +00:00
tg74
8b9d7be8e5 bugfix OS32
git-svn-id: branches/tg74/avx512@39719 -
2018-09-10 06:18:48 +00:00
tg74
1d9cbb4dcb new AVX512 opcodes
git-svn-id: branches/tg74/avx512@39705 -
2018-09-03 05:40:44 +00:00
tg74
5e1dc1a807 bugfix for test tasm9 32bit
git-svn-id: branches/tg74/avx512@39695 -
2018-09-01 08:26:18 +00:00
tg74
6f64177c6a bugfix avx512 OS32bit EVEX-coding
git-svn-id: branches/tg74/avx512@39661 -
2018-08-21 22:12:36 +00:00
tg74
29690162b8 bugfix OS32
git-svn-id: branches/tg74/avx512@39650 -
2018-08-19 18:41:45 +00:00
tg74
7c5cefad36 bugfix OS32
git-svn-id: branches/tg74/avx512@39648 -
2018-08-19 16:35:23 +00:00
tg74
7b8715184a bugfix OS32
git-svn-id: branches/tg74/avx512@39647 -
2018-08-19 16:31:09 +00:00
tg74
2b1da37d66 new avx512 instructions and bugfixes avx512
git-svn-id: branches/tg74/avx512@39636 -
2018-08-19 10:18:32 +00:00
tg74
867d145e50 support vector operand bcst,{sae},{er} + k-register
git-svn-id: branches/tg74/avx512@39457 -
2018-07-16 17:06:57 +00:00
tg74
4dc5442fa5 support vector operand writemask,zeroflag
git-svn-id: branches/tg74/avx512@39359 -
2018-07-02 20:20:03 +00:00
tg74
31e4d4ef5e AVX512 support for MMRegister xmm16..31 and ymm16..31, zmm0..31, vpaddsb support AVX512
git-svn-id: branches/tg74/avx512@39196 -
2018-06-08 06:53:35 +00:00
marco
f0042a4719 * vcmppd hardcoded primitives like vcmpeqpd.
* required increasing maxinfolen to 9 

git-svn-id: trunk@38404 -
2018-03-03 23:32:54 +00:00
florian
f66a91499d * FPC uses meanwhile more mov instructions, so extended taicpu.is_same_reg_move to support them
git-svn-id: trunk@38264 -
2018-02-17 09:45:19 +00:00
florian
31f78ea2b6 + implementation of the vectorcall calling convention by J. Gareth Moreton
+ tests

git-svn-id: trunk@38206 -
2018-02-11 17:50:37 +00:00
florian
e6a6938787 * make fpu/mmx/xmm/ymm registers numbers instead of flags to have enough space for zmm/bnd/k registers
git-svn-id: trunk@38116 -
2018-02-04 20:29:41 +00:00
nickysn
c464f7fa56 * fixed the SEG inline asm directive when used with 32-bit registers on the i8086 target
git-svn-id: trunk@37613 -
2017-11-22 15:04:30 +00:00
nickysn
8a0d8f025b * fixed another i8086 inline asm 32-bit constant bug (e.g. in 'or eax, 80000001h')
git-svn-id: trunk@37521 -
2017-10-25 19:38:37 +00:00
nickysn
325e66287c * fix for inline asm of instructions with 32-bit constant operands on i8086
git-svn-id: trunk@37519 -
2017-10-25 18:03:22 +00:00
nickysn
d7e4b50068 + also optimize x86_64 references by switching [rbp+reg64] to [reg64+rbp],
[r13+reg64] to [reg64+r13] and [r13d+reg32] to [reg32+r13d]

git-svn-id: trunk@37516 -
2017-10-24 16:18:43 +00:00
nickysn
5ae32a0ec5 + always do the x86_64 reference optimizations as if SS=DS, because the CPU
basically ignores these segments in long mode

git-svn-id: trunk@37515 -
2017-10-24 15:38:59 +00:00
nickysn
875339993f * strip segment overrides, for segments, which should be equal in the current
model to the default segment of the reference in optimize_ref, when
  inlineasm=false

git-svn-id: trunk@37511 -
2017-10-23 15:51:33 +00:00
nickysn
80226e3af4 + added an optimization pass, that optimizes x86 references
git-svn-id: trunk@37494 -
2017-10-20 15:55:55 +00:00
nickysn
67a0e9bdae + added x86 helper function get_default_segment_of_ref, which returns the
default segment base for the ref, in case there's no segment override
* in the internal assembler, use get_default_segment_of_ref to strip redundant
  prefixes, instead of always assuming all refs are DS-based

git-svn-id: trunk@37486 -
2017-10-18 14:24:58 +00:00
nickysn
6f2e64ff90 + added function get_ref_address_size
git-svn-id: trunk@37470 -
2017-10-16 14:13:03 +00:00
nickysn
b0653a6313 + added functions is_32_bit_ref and is_64_bit_ref, similar to is_16_bit_ref
* taicpu.needaddrprefix now uses is_32_bit_ref on x86_64
* is_16/32/64_bit_ref made part of the aasmcpu unit interface, so they can be
  used elsewhere (e.g. in the inline assembler readers)

git-svn-id: trunk@37469 -
2017-10-16 14:05:06 +00:00
nickysn
2b6e5d817e * changed the parameter of is_16_bit_ref to be a treference, instead of toper
git-svn-id: trunk@37463 -
2017-10-16 00:30:26 +00:00
nickysn
baf492c7a5 + another helper function: x86_parameterized_string_op_param_count
* when generating x86 code for parameterized string instructions with the
  internal object writer, don't rely on the destination operand being [(r/e)di]
  when determining the segment prefix, because when using intel syntax, source
  and destination can be anything (only the operand size, the address size and
  the source segment is taken into account)

git-svn-id: trunk@37452 -
2017-10-12 16:07:15 +00:00
nickysn
0fb79946a5 + added support for the parameterized versions of the x86 string instructions
(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
  and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
  is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
  with the 186+ 'ins' instruction.

git-svn-id: trunk@37446 -
2017-10-12 00:07:02 +00:00
nickysn
92a52a9f4d + implemented support for instructions with non-native address size on i8086
(16-bit and 32-bit), i386 (16-bit and 32-bit) and x86_64 (32-bit and 64-bit).
  Known bug: 32-bit addresses with an offset have their offset truncated to its
  low 16-bits on i8086

git-svn-id: trunk@37409 -
2017-10-06 15:27:14 +00:00
nickysn
8589b946fc * different versions (behind cpu specific ifdefs) of process_ea_ref renamed
process_ea_ref_64_32, process_ea_ref_32 and process_ea_ref_16, indicating
  the address size they support; this is done, so that in the future, we can
  mix them all on the same x86 architecture and support multiple address sizes

git-svn-id: trunk@37407 -
2017-10-05 22:15:26 +00:00
nickysn
31c9214884 * replaced R_SUBADDR with the appropriate size (R_SUBW, R_SUBD or R_SUBQ) in
the cpu specific process_ea_ref function

git-svn-id: trunk@37400 -
2017-10-05 20:39:32 +00:00
nickysn
e701fa8de1 * converted the x86 instruction flags to a set, so they can be extended more
easily and so that all the values are now available to the compiler
  (previously, there were several, which were mapped to the same value and thus
  were only used to make x86ins.dat easier to read)

git-svn-id: trunk@37299 -
2017-09-21 15:48:27 +00:00
florian
1ffdf02b94 + Ch_*Op4
+ op_const_reg_reg_reg

git-svn-id: trunk@36279 -
2017-05-21 11:12:55 +00:00
florian
b1dff29cbf * removed unused units
git-svn-id: trunk@36165 -
2017-05-09 19:53:14 +00:00
nickysn
0c244046a9 * proper register change info for the movs,cmps and scas x86 string instructions
(movsd still todo, because of the overlap with the sse2 instruction)

git-svn-id: trunk@35929 -
2017-04-23 21:30:25 +00:00
nickysn
1d34e96064 + added x86 instruction flag Ch_RFLAGScc, indicating instructions that read
specific bits from the flags register, according to their condition (used by
  Jcc/SETcc/CMOVcc)

git-svn-id: trunk@35907 -
2017-04-22 22:07:05 +00:00
nickysn
1146b7c12c + added detailed information for individual flag bits use for most x86
instructions. Not used by the compiler yet, but may allow more
  optimizations in the future.

git-svn-id: trunk@35882 -
2017-04-21 23:03:33 +00:00
nickysn
869f395a31 + added knowledge to the compiler for the x86 instructions, that don't read
their input registers, in case both parameters are the same register (e.g.
  xor eax, eax; sub eax, eax; etc.)

git-svn-id: trunk@35861 -
2017-04-20 15:11:56 +00:00
nickysn
9303a8f61a * changed the x86 TInsProp.Ch structure from a 3-element array to a pascal set;
this removes the limit of 3 Ch_XXX flags per instruction (thus allowing adding
  more precise flags, e.g. for tracking only certain bits of the flags register,
  etc.) and avoids the ugliness of having the Ch_None filler, which makes
  x86ins.dat less readable.

git-svn-id: trunk@35850 -
2017-04-19 16:48:35 +00:00
nickysn
189e49998c * fixes to the x86 instruction flags tracking attributes:
* AAA and AAS also read flags (AF)
  * CMC reads and writes flags (it inverts CF)
  * CMPSx and SCASx write flags
  * CMPSx, SCASx, LODSx, STOSx, MOVSx read the direction flag
  * NOT doesn't affect flags
  * REP isn't affected by and doesn't affect flags
  * REPE/REPNE/REPZ/REPNZ/REPC/REPNC don't write flags, only read them
  * ROL and ROR don't read flags
  * SAL doesn't read flags
  * SHLD and SHRD don't read flags

git-svn-id: trunk@35849 -
2017-04-19 15:42:50 +00:00
nickysn
3d28878210 + added taicpu.op_reg_reg_ref() constructor for x86, in order to support the
shld/shrd [ref],reg,CL instructions

git-svn-id: trunk@35832 -
2017-04-18 12:47:57 +00:00
Jonas Maebe
a25ebbba3e + added volatility information to all memory references
o separate information for reading and writing, because e.g. in a
     try-block, only the writes to local variables and parameters are
     volatile (they have to be committed immediately in case the next
     instruction causes an exception)
   o for now, only references to absolute memory addresses are marked
     as volatile
   o the volatily information is (should be) properly maintained throughout
     all code generators for all archictures with this patch
   o no optimizers or other compiler infrastructure uses the volatility
     information yet
   o this functionality is not (yet) exposed at the language level, it
     is only for internal code generator use right now

git-svn-id: trunk@34996 -
2016-11-27 18:17:37 +00:00
sergei
b5660401fe * Some cleanup for AVX part of internal assembler. Functionality is not changed.
git-svn-id: trunk@34948 -
2016-11-21 07:49:43 +00:00
sergei
ebe134febc * Fixed memory reference size for MOVSS instruction, Mantis #29954.
git-svn-id: trunk@34943 -
2016-11-21 03:31:25 +00:00
sergei
edf943a4f6 * Changed memory operand size for VMOVSS instruction to 32 bits, Mantis #29957.
git-svn-id: trunk@34918 -
2016-11-18 23:37:01 +00:00
florian
56252d59f0 + support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
git-svn-id: trunk@34917 -
2016-11-18 20:19:39 +00:00
pierre
38f751573a Copy TExternChain type and AddSymbol procedure to unit aasmcpu from agx86nsm unit
git-svn-id: trunk@34079 -
2016-07-06 06:55:31 +00:00
florian
ec92bc3390 * case of identifiers fixed
* x86-64 uses also the mov $0,... -> xor optimization

git-svn-id: trunk@33553 -
2016-04-24 20:01:43 +00:00