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5e6669890a
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246 Commits

Author SHA1 Message Date
pierre
5e6669890a Handle asmextraopt in powerpc, mips and sparc assemblers 
git-svn-id: trunk@26542 -
 2014-01-21 00:19:17 +00:00
sergei
ffba5aee60 * MIPS: emit PIC-friendly instruction sequences instead of "J" when fixing up branches outside of 128K range. Resolves #25399. 
git-svn-id: trunk@26215 -
 2013-12-11 10:56:07 +00:00
sergei
d72478eb64 * Function tjvmaddnode.cmpnode2topcmp is, in fact, not specific to any target. Moved it to generic tcgaddnode and reused in tmipsaddnode, where the same functionality was implemented in different way. 
git-svn-id: trunk@26151 -
 2013-11-28 11:52:47 +00:00
sergei
e16e19b170 * MIPS: removed specific handling of 32-bit shifts, generic code does the job just well. 
* Tweak 64-bit shifts to take advantage of 3-address instructions (i.e. don't operate on same register).

git-svn-id: trunk@26142 -
 2013-11-27 11:33:52 +00:00
sergei
2a112ad01b * MIPS: don't optimize reference twice for 64-bit loads and stores. Now loading/storing 64-bit value to global variable takes typically 3 instructions. 
git-svn-id: trunk@26139 -
 2013-11-25 14:27:35 +00:00
sergei
06735eaefc + MIPS peephole optimizer: eliminate redundant moves of floating point registers. 
git-svn-id: trunk@26136 -
 2013-11-25 13:57:19 +00:00
sergei
0bef197c84 * MIPS unary minus node: override the entire second_float method, not just emit_float_sign_change. Makes use of two-address neg.d/neg.s instructions, eliminating extra register moves. 
git-svn-id: trunk@26135 -
 2013-11-25 13:54:38 +00:00
pierre
a091c26750 * Use mips everywhere for big endian mips target 
git-svn-id: trunk@25992 -
 2013-11-07 21:38:43 +00:00
sergei
fbf6192aff * tmipsaddnode.second_addfloat: don't bother reusing locations, always allocate a new register for result. 
git-svn-id: trunk@25857 -
 2013-10-26 18:15:24 +00:00
sergei
dd472dbfb0 * MIPS: when converting int to real, use a floating point constant directly, instead of emulating it with integers. tai_real_64bit already handles all endian issues. 
git-svn-id: trunk@25856 -
 2013-10-26 18:12:25 +00:00
sergei
142d20ca30 * MIPS: cleanup assembler reader, MIPS references allow only a single register in parentheses. 
git-svn-id: trunk@25768 -
 2013-10-13 21:22:04 +00:00
sergei
e10e383b8e * MIPS: ".set macro"/".set nomacro" directives around ".cprestore" are necessary only when offset is outside smallint range. Otherwise they just clutter the assembler file. 
git-svn-id: trunk@25767 -
 2013-10-13 20:23:43 +00:00
svenbarth
c48d572996 Implement support for saving and restoring address registers. 
cgobj.pas, tcg:
  * g_save_registers: add the amount of used address registers to size as well
  * g_save_registers: save all used address registers
  * g_restore_registers: restore all stored address registers
m68k/cpubase.pas:
  * rename saved_standard_address_registers to saved_address_registers
all other platform's cpubase.{inc,pas} (except alpha, ia64 and vis which are not up to date):
  * add a saved_address_registers variable with one entry of RS_INVALID

At least a "make fullcycle" did complete.

git-svn-id: trunk@25664 -
 2013-10-05 21:43:42 +00:00
sergei
e7f6b06969 + MIPS internal linker: support TLS IE/LE and GPREL32 relocations, is now able to link tw14265. 
git-svn-id: trunk@25181 -
 2013-07-29 09:30:40 +00:00
sergei
404c3efa58 * MIPS: handle get_frame internally, so it sets pi_needs_stackframe flag on current procedure. This makes possible not to force pi_needs_stackframe on every procedure and thus omit saving/restoring $fp register when it is not necessary. 
git-svn-id: trunk@25170 -
 2013-07-24 15:25:12 +00:00
sergei
8e6d4b41e2 + MIPS: started the peephole optimizer. 
git-svn-id: trunk@25148 -
 2013-07-20 13:44:21 +00:00
sergei
9494fadf08 * MIPS: set pi_do_call flag for assembler procedures with stackframes, so in PIC mode it further receives pi_needs_got in PIC mode and allocates the GP save temp. 
* Deallocate GP save temp in epilogue to avoid warnings when compiled with -dEXTDEBUG
* g_concatcopy: don't check alignment, this allows single byte or word locations to be copied with 2 instructions. Larger unaligned references are supposed to be handled in g_concatcopy_unaligned instead.

git-svn-id: trunk@25147 -
 2013-07-20 13:42:41 +00:00
sergei
f80ce76a69 + MIPS: emulate "flags", i.e. support LOC_FLAGS location. This allows to generate differently optimized code for branching and for conversion to register, typically saving a register and instruction per compare. 
git-svn-id: trunk@25131 -
 2013-07-19 14:06:47 +00:00
sergei
9a6edd0fb8 * MIPS: handle restoring GP after calls without GAS macro processing, removes ugly workaround for GAS bug. 
git-svn-id: trunk@25130 -
 2013-07-19 08:04:06 +00:00
sergei
f49be98507 * MIPS: avoid temp if possible also when converting unsigned 32-bit integers to real. 
git-svn-id: trunk@25123 -
 2013-07-17 11:19:19 +00:00
sergei
c3350d13f9 * MIPS: floating point parameters on stack should be loaded to/from FPU registers directly, without using temp. 
git-svn-id: trunk@25122 -
 2013-07-17 11:00:46 +00:00
sergei
e82ecd66f3 - MIPS: removed target-specific real_to_real conversion, generic code handles it just well. 
git-svn-id: trunk@25083 -
 2013-07-11 08:28:24 +00:00
sergei
1ca2a253e8 MIPS, improved integer to real conversions: 
* Use fpc_[int64|qword]_to_double instead of [int64|qword]_to_float64, makes RTL no longer dependent on softfloat code.
* Move 32-bit values from integer registers to FPU registers without using memory.
* Fixed branching, was still using a macro and delay slot was missing.

git-svn-id: trunk@25071 -
 2013-07-09 14:17:51 +00:00
sergei
faa778b6c7 * MIPS: div/mod and 32-bit shifts: don't bother reusing argument locations, always allocate new register and emit 3-address instructions. 
* Fixed possible overwrite of LOC_CREGISTER numerator in optimized division by power of 2.

git-svn-id: trunk@25066 -
 2013-07-08 11:51:39 +00:00
sergei
9e4cc57768 * MIPS: handle 8 and 16-bit arithmetic shifts internally, by shifting argument left by 24/16 bits, followed with 32-bit arithmetic shift right by appropriately adjusted amount. 
This approach should be usable for other non-x86 targets as well.

git-svn-id: trunk@25062 -
 2013-07-08 08:45:16 +00:00
sergei
59d6df4fca * MIPS: replaced opcode mapping functions with array, much shorter that way. Separate "overflow" mapping is also no longer needed. 
* Use SRAV/SRLV/SLLV opcodes for shifts by variable amount.

git-svn-id: trunk@25038 -
 2013-07-04 14:26:44 +00:00
sergei
1c84c3edbf * Fixed label optimizer to work with MIPS, and enabled level 1 optimization for MIPS targets. 
The difference in branch instruction formats is isolated in function JumpTargetOp, it is a plain function rather than a virtual method, so it can be easily inlined and, after inlining, produces the same code for non-MIPS targets as it was before change.

git-svn-id: trunk@25033 -
 2013-07-03 14:40:24 +00:00
sergei
8823574fe2 * MIPS: get rid of DIV and DIVU macros. 
git-svn-id: trunk@25030 -
 2013-07-02 14:28:10 +00:00
sergei
d0ae800da6 + MIPS: Use INS and EXT instructions for bit manipulations when target CPU type is set to mips32r2. 
git-svn-id: trunk@25029 -
 2013-07-02 14:21:29 +00:00
sergei
828309e61d - MIPS: removed opcodes that are not in any known documentation. 
git-svn-id: trunk@25023 -
 2013-07-01 06:09:53 +00:00
sergei
7810d6637a * MIPS: improved 64-bit comparisons by using cg.a_cmp_reg_reg_label, uses less instructions and registers when comparing with zero. 
git-svn-id: trunk@25008 -
 2013-06-28 15:46:17 +00:00
sergei
7a28815182 * r24895 used wrong expression for swapping sides of comparison, and it went undetected by tests. Fixed. 
git-svn-id: trunk@25007 -
 2013-06-28 15:40:37 +00:00
sergei
c855868a3d * MIPS: get rid of macros in comparison operations, use immediate operands for comparison with constants when possible. 
+ InternalError if valid GP is needed but pi_needs_got was not set in pass 1.

git-svn-id: trunk@25003 -
 2013-06-28 10:22:26 +00:00
sergei
89c9cdf6c4 + MIPS: implemented parameter location reusing, eliminating second copy of (potentially large) records passed by value. When parameter is passed both in registers and stack, let it have a single LOC_REFERENCE location on callee side, and store relevant registers on stack (into 16-byte area reserved by ABI) early in prologue. 
git-svn-id: trunk@24970 -
 2013-06-25 08:15:17 +00:00
sergei
456f991c51 * MIPS: 3-operand forms of DIV and DIVU are not macros if first operand is $zero. 
git-svn-id: trunk@24918 -
 2013-06-20 13:14:38 +00:00
sergei
121271c38f * MIPS case node: simplified code a bit. 
* Moved jump tables into data segment. For disassembly-based stack unwinding to work properly, MIPS ABI expects text segment to contain instructions only.

git-svn-id: trunk@24904 -
 2013-06-15 12:36:21 +00:00
sergei
5bcae5a80a - Removed TMIPSParaManager.getintparaloc method, its generic implementation from r24716 works without issues. 
git-svn-id: trunk@24903 -
 2013-06-15 12:24:19 +00:00
sergei
8b8553991a + MIPS: prevent coalescing written-to registers with $sp,$fp,$zero and $at. 
+ Implemented subset of "spill replace" functionality, replacing moves from/to spilled registers with loads/stores to spill locations. This helps to reduce amount of instructions.

git-svn-id: trunk@24900 -
 2013-06-15 04:04:08 +00:00
sergei
6a8e4f0381 * MIPS: generate real instructions, not macros, for comparisons with $zero. 
* g_concatcopy, g_concatcopy_unaligned: call a_cmp_reg_reg_label instead of duplicating code.

git-svn-id: trunk@24895 -
 2013-06-14 07:27:48 +00:00
sergei
fb88cc4257 * TCGMIPS.a_load_reg_reg: reduce code duplication, and don't generate same register move for OS_32->OS_S32 and vice versa. Such moves explode into at least 4 instructions if register needs spilling, after which they are no longer recognized and cannot be removed by reg.allocator. So it's much better not to generate them in first place. 
* Implemented overflow checking for multiplication, no longer generate MULO and MULOU macros.

git-svn-id: trunk@24894 -
 2013-06-14 00:12:17 +00:00
sergei
7e0ae2e984 * MIPS: fixed cgsize2subreg to return correct result for float registers. 
- TCGMIPS.getfpuregister override is no longer necessary with the above fix.

git-svn-id: trunk@24893 -
 2013-06-13 23:50:20 +00:00
sergei
562714129f * MIPS: get completely rid of LI macro, generate equivalent CPU instructions instead. 
git-svn-id: trunk@24862 -
 2013-06-10 02:07:21 +00:00
sergei
86637a9ff9 * MIPS: pi_needs_got is necessary when doing unsigned to float conversions (it uses a global constant) and also if procedure does any calls in PIC mode. 
git-svn-id: trunk@24822 -
 2013-06-08 23:29:50 +00:00
sergei
2868a30cce + Added mips32r2 opcodes needed for pic32. 
* Output registers of type R_SPECIALREGISTER as numbers.
+ For MTC0/MFC0 instructions, set type of first operand to R_SPECIALREGISTER, since it designates a coprocessor register.

git-svn-id: trunk@24799 -
 2013-06-03 20:01:30 +00:00
Jonas Maebe
9938169d2c * don't use the paracgsize in get_paraloc_def(), because it generally 
contains the tcgsize of the entire parameter rather than only of
    what is left (-> calculate it from the remaining parameter length)

git-svn-id: trunk@24776 -
 2013-06-02 14:05:07 +00:00
sergei
4b820a1ca5 - Removed tcgloadnode.generate_picvaraccess, it is never used and is not necessary because PIC stuff is handled at lower levels. 
git-svn-id: trunk@24764 -
 2013-06-02 10:49:17 +00:00
Jonas Maebe
7566ddcc8f * add a tdef to each parameter location and set it for all target 
backends (not yet used, will be used in high level code generator)

git-svn-id: trunk@24761 -
 2013-06-02 10:24:02 +00:00
sergei
fe322f35d5 * MIPS: fixed passing CPU type specified with -CpXXX switch to assembler 
- removed mips_cpu variable and cpu_mips_default CPU type.
  * globals.pas: default CPU type changed to MIPS2, this is what was passed to assembler before.

git-svn-id: trunk@24643 -
 2013-05-30 15:02:40 +00:00
sergei
0ad96d2099 * MIPS: some clean up of assembler reader: 
- references cannot be in brackets
  - registers are only prefixed by dollar, never by percent
  - syntax x@LO is not supported, must be %lo(x).

git-svn-id: trunk@24633 -
 2013-05-30 09:28:21 +00:00
sergei
2944fc8839 * MIPS improvements: 
* reworked condition codes, changed BC1T and BC1F from separate instructions to condition jumps.
  - removed A_P_SW, A_P_LW and A_SPARC8UNIMP
  + support '.set at' and '.set noat' directives
  + prepare to support bgtz,bgez,bltz,blez instructions.

git-svn-id: trunk@24631 -
 2013-05-29 17:35:56 +00:00