florian
8943c0584e
+ patch by J. Gareth Moreton to support BMI2 instructions
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+ extended avx test generator with the newly added BMI2 instructions
git-svn-id: trunk@39875 -
2018-10-07 10:10:19 +00:00
florian
64ad48e89e
* forgotten part of r39750
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git-svn-id: trunk@39752 -
2018-09-13 20:20:40 +00:00
florian
78943ea843
+ patch by J. Gareth Moreton: x86 optimisations for Jcc and SETcc, resolves #33899
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* optimization also added for i386
git-svn-id: trunk@39307 -
2018-06-25 20:40:05 +00:00
Jonas Maebe
4686f61002
* keep track of the temp position separately from the offset in references,
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so that they can still be freed after the reference has been changed
(e.g. in case of array indexing or record field accesses) (mantis #33628 )
git-svn-id: trunk@38814 -
2018-04-22 17:03:16 +00:00
nickysn
518cdf9674
* replaced the saved_XXX_registers arrays with virtual methods inside
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tcpuparamanager, very similar to the existing get_volatile_registers_XXX. The
new methods are called get_saved_registers_XXX, where XXX is the register
type ("int", "address", "fpu" or "mm")
git-svn-id: trunk@38794 -
2018-04-19 21:22:16 +00:00
florian
25c5ee2fc3
* patch by J. Gareth Moreton to fix vectorcall (no effect) for linux,
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resolves #33184 and #33542
git-svn-id: trunk@38663 -
2018-04-02 21:14:26 +00:00
florian
8b0bbdcaab
* fix flag subregs after r38206
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git-svn-id: trunk@38502 -
2018-03-11 20:30:11 +00:00
florian
9b18e39c81
* enable Lea2AddBase and Lea2AddIndex in TX86AsmOptimizer.PostPeepholeOptLea as we have flag tracking now
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* some flag allocations fixed
git-svn-id: trunk@38501 -
2018-03-11 20:30:09 +00:00
florian
5fbecc5501
+ use TX86AsmOptimizer.OptPass1SHLSAL on x86-64
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git-svn-id: trunk@38499 -
2018-03-11 14:35:22 +00:00
marco
f0042a4719
* vcmppd hardcoded primitives like vcmpeqpd.
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* required increasing maxinfolen to 9
git-svn-id: trunk@38404 -
2018-03-03 23:32:54 +00:00
marco
f21a141144
* mantis #32001 , add 32 vcmpps variants.
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git-svn-id: trunk@38403 -
2018-03-03 23:10:03 +00:00
florian
8c5606b41d
+ support mmx shifting
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git-svn-id: trunk@38367 -
2018-02-27 21:40:12 +00:00
florian
3b779278e2
+ (slightly) patch by Emelyanov Roman to add support of SEH directive in FPC internal assembler with INTEL syntax, resolves #29894
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git-svn-id: trunk@38331 -
2018-02-24 16:14:08 +00:00
florian
91514da267
* factored out TX86AsmOptimizer.PostPeepholeOptCall
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+ use TX86AsmOptimizer.PostPeepholeOptCall on x86-64
git-svn-id: trunk@38278 -
2018-02-17 23:25:01 +00:00
florian
112373a124
* fix passing floats on unix after vectorcall patch
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git-svn-id: trunk@38209 -
2018-02-11 17:50:43 +00:00
florian
31f78ea2b6
+ implementation of the vectorcall calling convention by J. Gareth Moreton
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+ tests
git-svn-id: trunk@38206 -
2018-02-11 17:50:37 +00:00
florian
810acd82b2
* patch by J. Gareth Moreton that makes some improvements to the Peephole Optimizer for x86 and x86-64 code, as well as some cleanup with formatting, code syntax consistency, and debug messages.
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- xorq %reg,%reg (identical registers) is now changed to xorl %reg,%reg if doing so removes the REX prefix.
- movw %bx,%ax; andl $0xffff,%eax, for example, is now changed to movzwl %bx,%eax as long as a conditional operation doesn't follow 'and' (checks to see if the CPU flags are in use).
- movzbq and movzwq get optimised to movzbl and movzwl respectively if doing so removes the REX prefix.
- Removal of optimisation code that zero-extends from 32-bit to 64-bit, because there isn't actually a valid combination of opcodes for MOVZX that allows that (for registers,
just use MOV). This is not the case with MOVSX.
- movq is now optimised to movl even if the CPU flags are in use (this stops mov %reg,0 from being optimised to xor %reg,%reg if doing so breaks an algorithm that relies on them).
- Fixed typo in peephole message regarding movq to movl (it said movd instead).
- Made the peephole debug messages more consistent in formatting, some of which now have more detail.
* small fixes of the patch
git-svn-id: trunk@38070 -
2018-01-28 14:41:54 +00:00
florian
73fda1ccb6
* factored out OptPass1Sub
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+ make use of OptPass1Sub on x86_64 and i8086 as well
git-svn-id: trunk@37572 -
2017-11-10 20:55:22 +00:00
nickysn
ae92973196
+ added support for the retw, retnw, retfw, retd, retnd, retfd, retq, retnq and
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retfq x86 instructions. These are variants of the ret instruction with the
return offset size set explicitly, e.g. retfw is a 16-bit far ret (i.e. pops
a 16-bit offset and a 16-bit segment), retfd is a 32-bit far ret (pops a
32-bit offset, followed by a 16-bit segment), etc.
git-svn-id: trunk@37571 -
2017-11-10 16:53:29 +00:00
pierre
ba3afefa4c
Regenerate register include files after commit 37564: Fix value of NR_DR6 and NR_DR7
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git-svn-id: trunk@37565 -
2017-11-07 07:30:42 +00:00
florian
4da4b768ec
* factored out PostPeepholeOptTest
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+ use PostPeepholeOptTest on x86-64
git-svn-id: trunk@37551 -
2017-11-04 19:10:14 +00:00
florian
3097eaf8ee
* made PostPeepholeOptMov a function
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git-svn-id: trunk@37550 -
2017-11-04 19:10:12 +00:00
florian
a7ea7fb569
* factored out PostPeepholeOptCmp
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+ use PostPeepholeOptCmp for x86_64
git-svn-id: trunk@37549 -
2017-11-04 19:10:09 +00:00
nickysn
80226e3af4
+ added an optimization pass, that optimizes x86 references
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git-svn-id: trunk@37494 -
2017-10-20 15:55:55 +00:00
nickysn
e8bbc4eef9
+ support the xlat x86 instruction syntax with a memory operand. This allows
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specifying the address size (e.g. xlat byte ptr [bx] or xlat byte ptr [ebx])
git-svn-id: trunk@37478 -
2017-10-17 16:40:06 +00:00
nickysn
0fb79946a5
+ added support for the parameterized versions of the x86 string instructions
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(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
with the 186+ 'ins' instruction.
git-svn-id: trunk@37446 -
2017-10-12 00:07:02 +00:00
nickysn
92a52a9f4d
+ implemented support for instructions with non-native address size on i8086
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(16-bit and 32-bit), i386 (16-bit and 32-bit) and x86_64 (32-bit and 64-bit).
Known bug: 32-bit addresses with an offset have their offset truncated to its
low 16-bits on i8086
git-svn-id: trunk@37409 -
2017-10-06 15:27:14 +00:00
florian
198c53a908
o patch by J. Gareth "Kit" Moreton, resolves partially issue #32037
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* generate instructions with shorter imm on x86-64 if possible
git-svn-id: trunk@37376 -
2017-10-01 18:40:09 +00:00
florian
15b617546e
+ call TX86AsmOptimizer.OptPass1VOP for logical operations as well
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git-svn-id: trunk@37367 -
2017-10-01 14:40:21 +00:00
nickysn
aec03309ef
+ added CPUX86_HAS_SSE2 to x86 tcpuflags
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git-svn-id: trunk@37326 -
2017-09-26 16:02:56 +00:00
nickysn
e701fa8de1
* converted the x86 instruction flags to a set, so they can be extended more
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easily and so that all the values are now available to the compiler
(previously, there were several, which were mapped to the same value and thus
were only used to make x86ins.dat easier to read)
git-svn-id: trunk@37299 -
2017-09-21 15:48:27 +00:00
nickysn
ab62e2237b
* mark the sldt,syscall,sysenter,sysexit,sysret,andn,bextr,rorx,sarx,shlx and
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shrx instructions as protected mode only
git-svn-id: trunk@37275 -
2017-09-20 15:43:23 +00:00
florian
05ecd784f2
* factored out OptPass1LEA and use it for x86-64 as well
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+ LEAMov2LEA optimization
git-svn-id: trunk@37199 -
2017-09-13 20:40:32 +00:00
florian
22956c4393
+ TX86AsmOptimizer.OptPass1OP
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git-svn-id: trunk@36365 -
2017-05-28 13:49:43 +00:00
florian
912e6d129a
* fix modification flags for *ROUND*
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git-svn-id: trunk@36280 -
2017-05-21 11:12:57 +00:00
florian
0f16f6d94d
+ OptPass1MOVXX
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git-svn-id: trunk@36209 -
2017-05-14 20:59:10 +00:00
florian
535c990233
+ OptPass1MOVAP
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git-svn-id: trunk@36203 -
2017-05-13 21:48:44 +00:00
florian
b1dff29cbf
* removed unused units
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git-svn-id: trunk@36165 -
2017-05-09 19:53:14 +00:00
florian
52d3756c26
* factored out OptPass1Movx and merged i386 and x86-64 version
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git-svn-id: trunk@36159 -
2017-05-08 20:44:27 +00:00
florian
06c4c651fd
* factored out PrePeepholeOptSxx
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+ x86-64 uses PrePeepholeOptSxx now as well
git-svn-id: trunk@36158 -
2017-05-08 20:44:24 +00:00
florian
4a43d992f5
* unified usage of MatchOpType
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* fixed generic MatchOpType
git-svn-id: trunk@36145 -
2017-05-07 16:18:33 +00:00
florian
7afe762d22
* factored out OptPass2Jcc assembler optimization
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* OptPass2Jcc now used by x86-64 as well
* remove orphaned alignments if the label is not used anymore after cmov is used
git-svn-id: trunk@36143 -
2017-05-07 12:45:48 +00:00
florian
e3f0b338d4
* SkipLabels moved to aoptutils
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* factored out OptPass2Jmp assembler optimization
* OptPass2Jmp now used by x86-64 as well
git-svn-id: trunk@36141 -
2017-05-06 21:07:02 +00:00
nickysn
af48d176ec
+ precise flag information for the ucomiss,ucomisd,vucomiss and vucomisd x86 instructions
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git-svn-id: trunk@36115 -
2017-05-05 13:41:43 +00:00
nickysn
ff1ee6836d
+ fix RegReadByInstruction for the x86 MOVSD instruction
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git-svn-id: trunk@35968 -
2017-04-27 14:42:08 +00:00
nickysn
c8487c4150
+ added individual bits of the x86 flags register as subregisters
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git-svn-id: trunk@35955 -
2017-04-26 13:52:52 +00:00
nickysn
5f66f5cebb
+ distinguish between x86 flags subregisters: flags, eflags and rflags
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git-svn-id: trunk@35953 -
2017-04-25 16:10:43 +00:00
nickysn
0c244046a9
* proper register change info for the movs,cmps and scas x86 string instructions
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(movsd still todo, because of the overlap with the sse2 instruction)
git-svn-id: trunk@35929 -
2017-04-23 21:30:25 +00:00
nickysn
1d34e96064
+ added x86 instruction flag Ch_RFLAGScc, indicating instructions that read
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specific bits from the flags register, according to their condition (used by
Jcc/SETcc/CMOVcc)
git-svn-id: trunk@35907 -
2017-04-22 22:07:05 +00:00
nickysn
1146b7c12c
+ added detailed information for individual flag bits use for most x86
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instructions. Not used by the compiler yet, but may allow more
optimizations in the future.
git-svn-id: trunk@35882 -
2017-04-21 23:03:33 +00:00