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9dc8744b53
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Author SHA1 Message Date
nickysn
9dc8744b53 - removed debug writeln 
git-svn-id: branches/z80@44580 -
 2020-04-04 20:15:10 +00:00
nickysn
59d7a45215 * generate more optimal code for unsigned 8-bit comparisons in TZ80AddNode.second_cmp 
git-svn-id: branches/z80@44579 -
 2020-04-04 20:14:31 +00:00
nickysn
5585bdb6aa + also support unsigned 8-bit > and <= in TZ80AddNode.second_cmp. All 8-bit unsigned comparisons now 
work.

git-svn-id: branches/z80@44576 -
 2020-04-04 17:49:13 +00:00
nickysn
f52f9dc56b + added a not-yet-complete implementation of TZ80AddNode.second_cmp. Only 8-bit unsigned comparison 
works for now, and only for the <,= and <> operators

git-svn-id: branches/z80@44575 -
 2020-04-04 17:15:31 +00:00
nickysn
3ed692a157 + implemented tcgz80.a_jmp_flags 
git-svn-id: branches/z80@44574 -
 2020-04-04 17:07:54 +00:00
nickysn
ff655543ed + support conditional jumps in the sdcc-sdasz80 assembler writer 
git-svn-id: branches/z80@44573 -
 2020-04-04 17:05:49 +00:00
nickysn
d05a632616 + write jump operands (not all forms supported yet) in the sdcc-sdasz80 asm output 
git-svn-id: branches/z80@44572 -
 2020-04-04 16:59:14 +00:00
nickysn
fb3a079916 * updated TAsmCond and TResFlags for the Z80 
git-svn-id: branches/z80@44571 -
 2020-04-04 16:12:47 +00:00
nickysn
99e304165e * fix for 64-bit OP_AND/OP_OR/OP_XOR in tcgz80.a_op_reg_reg_internal 
git-svn-id: branches/z80@44570 -
 2020-04-04 15:33:01 +00:00
nickysn
c0b3eb70ac + fix for 64-bit OP_NOT in tcgz80.a_op_reg_reg_internal 
git-svn-id: branches/z80@44569 -
 2020-04-04 15:30:43 +00:00
nickysn
5b8fd51b3a + implemented OP_NEG in tcgz80.a_op_reg_reg_internal 
git-svn-id: branches/z80@44568 -
 2020-04-04 15:27:28 +00:00
nickysn
a362c3247d + added instruction encoding info for all the remaining Z80 instructions 
git-svn-id: branches/z80@44567 -
 2020-04-04 13:49:07 +00:00
nickysn
c5aa1193bf + started describing the instructions encoding 
git-svn-id: branches/z80@44558 -
 2020-04-04 02:35:15 +00:00
nickysn
4027ad18e0 + added strict validation for the param types in z80ins.dat 
git-svn-id: branches/z80@44557 -
 2020-04-04 02:11:20 +00:00
nickysn
20eab5582f + generate the Z80 instruction enum and string table from z80ins.dat via a newly created tool 
git-svn-id: branches/z80@44556 -
 2020-04-04 01:36:07 +00:00
nickysn
6a2dbad8ca * synchronize with trunk 
git-svn-id: branches/z80@44555 -
 2020-04-04 00:36:08 +00:00
nickysn
565cc0e96b + created a parseable Z80 instruction description file, very loosely based on x86ins.dat. Parser not 
implemented yet, but will be soon.

git-svn-id: branches/z80@44554 -
 2020-04-04 00:21:50 +00:00
nickysn
9309e2c42e * replace 'add/adc/sub/sbc/and/or/xor/cp orgreg' with 'add/adc/sub/sbc/and/or/xor/cp spilltemp' in 
trgcpu.do_spill_replace

git-svn-id: branches/z80@44553 -
 2020-04-03 22:42:02 +00:00
nickysn
e43834c5d0 * replace 'inc/dec orgreg' with 'inc/dec spilltemp' in trgcpu.do_spill_replace 
git-svn-id: branches/z80@44552 -
 2020-04-03 22:19:40 +00:00
florian
96a368fdf9 * building on non-x86/non-xtensa fixed 
git-svn-id: trunk@44551 -
 2020-04-03 20:40:36 +00:00
florian
a6cfaa996a * few cleanups towards building the z80-embedded system unit 
git-svn-id: branches/z80@44550 -
 2020-04-03 20:37:27 +00:00
florian
d723b69325 * regenerated 
git-svn-id: branches/z80@44549 -
 2020-04-03 20:37:03 +00:00
florian
7ec42f5dc2 * merge artefacts removed 
git-svn-id: branches/z80@44548 -
 2020-04-03 20:31:51 +00:00
florian
89741ddeb5 * lazarus version updated 
git-svn-id: branches/z80@44547 -
 2020-04-03 20:25:47 +00:00
florian
0fc1ba26f8 * compilation fixed 
git-svn-id: branches/z80@44546 -
 2020-04-03 20:25:31 +00:00
florian
3705f95b92 * compilation fixed 
git-svn-id: trunk@44545 -
 2020-04-03 20:15:27 +00:00
florian
6c6a16a154 + xtensa-linux 
git-svn-id: trunk@44544 -
 2020-04-03 20:15:26 +00:00
florian
af8202be3d * compilation for non-Xtensa targets fixed 
git-svn-id: trunk@44543 -
 2020-04-03 20:15:26 +00:00
florian
fc98a0db4f * cosmetics 
git-svn-id: trunk@44542 -
 2020-04-03 20:15:25 +00:00
florian
c1c201f93c * Xtensa: fix passing of floating point parameters 
git-svn-id: trunk@44541 -
 2020-04-03 20:15:24 +00:00
florian
66cbee5e31 * factor out first_addfloat_soft 
git-svn-id: trunk@44540 -
 2020-04-03 20:15:24 +00:00
florian
fa4cbc89a5 + Xtensa: hard float support, i.e. make use of floating point extension if available 
git-svn-id: trunk@44539 -
 2020-04-03 20:15:23 +00:00
florian
ba3de67f3b + Xtensa: the boolean extension is used as flags 
git-svn-id: trunk@44538 -
 2020-04-03 20:15:22 +00:00
nickysn
9d545342f8 * replace 'add/adc/sub/sbc/and/or/xor/cp A,orgreg' with 'add/adc/sub/sbc/and/or/xor/cp A,spilltemp' in trgcpu.do_spill_replace 
git-svn-id: branches/z80@44537 -
 2020-04-03 20:05:42 +00:00
nickysn
a58bab4318 + replace 'ld orgreg,const' with 'ld spilltemp,const' in trgcpu.do_spill_replace 
git-svn-id: branches/z80@44536 -
 2020-04-03 19:47:47 +00:00
nickysn
fe3f4a7447 * fixes in trgcpu.do_spill_replace 
git-svn-id: branches/z80@44535 -
 2020-04-03 19:41:39 +00:00
nickysn
8ceee70912 * range check for spilltemp.offset in [-128..127], not [0..63] in trgcpu.do_spill_replace for Z80 
git-svn-id: branches/z80@44534 -
 2020-04-03 19:32:10 +00:00
nickysn
8291d24b7f * fix comment 
git-svn-id: branches/z80@44533 -
 2020-04-03 18:53:52 +00:00
nickysn
bf8d560cc6 * treat all Z80 registers as 8-bit 
git-svn-id: branches/z80@44532 -
 2020-04-03 18:53:10 +00:00
ondrej
7cecc87441 odbc: use ftBlob only for VARBINARY(MAX) fields 
git-svn-id: trunk@44531 -
 2020-04-03 11:01:45 +00:00
ondrej
0c8cf3e323 odbc: use ftBlob also for SQL_VARBINARY fields because they can have size bigger than max allowed size for ftVarBytes (High(Word)) 
git-svn-id: trunk@44530 -
 2020-04-03 09:47:31 +00:00
marco
e53b67517a * improve porunidle casing, suggestion by Bart. 
git-svn-id: trunk@44529 -
 2020-04-03 08:47:54 +00:00
nickysn
5ddd0dd9b8 + implemented a_load_const_ref for more efficient Z80 code generation for const assignment to local variables 
git-svn-id: branches/z80@44528 -
 2020-04-03 02:23:05 +00:00
nickysn
4fe04ac53a * write references of the type (IX+const), (IY+const) as const(IX) or const(IY), since that appears to 
be what sdcc-sdasz80 accepts

git-svn-id: branches/z80@44527 -
 2020-04-03 01:33:41 +00:00
nickysn
4099c0eed8 + initial implementation (not working yet) for spilling_create_store and spilling_create_load for Z80 
git-svn-id: branches/z80@44526 -
 2020-04-03 01:03:49 +00:00
nickysn
e04d2acd6c + emit references with negative offsets correctly in the sdcc-sdasz80 asm output 
git-svn-id: branches/z80@44525 -
 2020-04-03 00:54:22 +00:00
nickysn
4de1d5a8bf + Z80 stackframe generation 
git-svn-id: branches/z80@44524 -
 2020-04-03 00:15:24 +00:00
nickysn
574fea7e63 + ait_tempalloc asm output for sdcc-sdasz80 
git-svn-id: branches/z80@44523 -
 2020-04-02 23:29:52 +00:00
nickysn
4b281dd6c9 * changed the ifndef avr to ifdef avr in GetNextReg 
git-svn-id: branches/z80@44522 -
 2020-04-02 23:05:49 +00:00
nickysn
71cadc0a3e * moved the AVR-specific comment next to the AVR specific code 
git-svn-id: branches/z80@44521 -
 2020-04-02 23:04:45 +00:00