Commit Graph

26 Commits

Author SHA1 Message Date
Jonas Maebe
a0f850d57f * synchronised with trunk till r41885
git-svn-id: branches/debug_eh@41886 -
2019-04-16 16:20:44 +00:00
Jeppe Johansen
2b78a8fd3d - Add support for .option directive in riscv assembler.
- Use addiw when adjusting U32 to S32

git-svn-id: trunk@41870 -
2019-04-14 20:51:29 +00:00
Jonas Maebe
a079e5fa80 * synchronised with trunk till r41449
git-svn-id: branches/debug_eh@41450 -
2019-02-24 20:01:53 +00:00
Jonas Maebe
07bd4ba517 * let all the case code generation work with tconstexprint instead of aint,
so it also works for 32 bit targets and a high level code generator
    (where aint is still 32 bit, but 64 bit operations are not decomposed)

git-svn-id: trunk@41441 -
2019-02-24 19:58:37 +00:00
Jonas Maebe
4cd6f59bc3 * changed create_hlcodegen into a procvar, so that we don't have to insert
hlcgllvm in the uses clause of every unit that calls create_hlcodegen
   o prevents dependency cycles that can cause llvm codegen units to init
     before the cpu variants, which is bad since the llvm versions have to
     override the cpu variants in their init code (+ added checks in the
     init code that they are in fact initialised later)

git-svn-id: branches/debug_eh@40410 -
2018-11-29 21:31:15 +00:00
pierre
11851d274c Fix riscv32 compilation error introduced in last commit
git-svn-id: trunk@40323 -
2018-11-16 10:24:27 +00:00
pierre
7c92412c74 Avoid overflow error in riscv code generator
git-svn-id: trunk@40318 -
2018-11-15 16:57:57 +00:00
Jonas Maebe
1a9eb77698 * fixed compilation with -O3 (one false positive, one real error)
git-svn-id: trunk@40155 -
2018-11-01 20:39:38 +00:00
pierre
aa89182bf5 Fix compilation with -dEXTDEBUG
git-svn-id: trunk@39923 -
2018-10-13 11:34:53 +00:00
Jeppe Johansen
d33b520690 Clean up peephole optimization code.
Add hardfloat ABI option for RiscV. Still needs proper implementation though.
Add CG support for profiling.

git-svn-id: branches/laksen/riscv_new@39798 -
2018-09-24 17:15:22 +00:00
Jeppe Johansen
576ef934bd Fix bug in lui+addi immediate load for spilling code.
git-svn-id: branches/laksen/riscv_new@39764 -
2018-09-16 20:51:15 +00:00
Jeppe Johansen
74a7963d58 Redo overflow checking code.
Fix shift operators in case of unsigned subreg operations. There should be no sign extension here.
Add some unittest implementations that test stack execution and writing to readonly constants.

git-svn-id: branches/laksen/riscv_new@39762 -
2018-09-16 18:37:59 +00:00
Jeppe Johansen
29ea4ed07d Add rounding mode operands.
Add support for trunc and round methods.

git-svn-id: branches/laksen/riscv_new@39698 -
2018-09-01 19:48:44 +00:00
Jeppe Johansen
2af0ca8546 Fix bugs caused by swapping of operands in float comparisons.
git-svn-id: branches/laksen/riscv_new@39697 -
2018-09-01 19:47:28 +00:00
florian
4f052e4f90 o fix several issues with floating point exceptions
+ mask underflow and precision on startup
  + check for floating point exceptions after inlined float routine helpers
  - do not check for floating point exceptions after floating point moves 

git-svn-id: branches/laksen/riscv_new@39645 -
2018-08-19 15:26:00 +00:00
florian
999cbd94b8 + support to generate software based floating point exception checking
(enabled by -CE)

git-svn-id: branches/laksen/riscv_new@39639 -
2018-08-19 10:56:47 +00:00
Jeppe Johansen
f781c8942e Write real atomic operations, and add memory barrier operations.
Add support for fence, and acquire/release syntax to assembler reader.
Fix broken register aliases.

git-svn-id: branches/laksen/riscv_new@39524 -
2018-07-29 16:43:09 +00:00
Jeppe Johansen
a8c82856b1 Fixed missing maybeadjust calls after not operation.
git-svn-id: branches/laksen/riscv_new@39493 -
2018-07-23 10:20:32 +00:00
Jeppe Johansen
b98eb3daa9 Changed order in stack unravelling RTL code, to match the most common cases.
Fixed unsigned conditions for branch conditions.
Added some additional const loading cases.
Changed the temporary register used during calls because it could otherwise clash with the argument passing registers.

git-svn-id: branches/laksen/riscv_new@39492 -
2018-07-23 01:11:31 +00:00
Jeppe Johansen
c6b27bc225 Fix shift operations on 32bit operands.
git-svn-id: branches/laksen/riscv_new@39489 -
2018-07-22 19:25:46 +00:00
Jeppe Johansen
6d9a0fdc73 Added implementation of InstructionLoadsFromReg.
Fixed spilling_get_operation_type_ref, no mem operation modifies ref registers.

git-svn-id: branches/laksen/riscv_new@39487 -
2018-07-22 18:38:07 +00:00
Jeppe Johansen
a906feb05e Fixed bug in peephole optimizer.
git-svn-id: branches/laksen/riscv_new@39486 -
2018-07-22 16:58:10 +00:00
Jeppe Johansen
2499129ba5 Pass aggregates larger than 2*XLEN as a reference.
Fix load_reg_reg and make it do proper type conversions.
Added maybeadjust to tcgrv.

git-svn-id: branches/laksen/riscv_new@39485 -
2018-07-22 14:15:29 +00:00
Jeppe Johansen
054bf32f1f Add RV64GC cpu type.
Fix float loading.
Fix a number of small issues with wrong operand sizes.
Fixed concatcopy code generation.
Align jump table for case statements.

git-svn-id: branches/laksen/riscv_new@39481 -
2018-07-21 22:34:42 +00:00
Jeppe Johansen
6352328f3a Update packages with information about RiscV.
Fix g_external_wrapper, since it uses a register.
Fixed calling of gas.
Ported cprt0.

git-svn-id: branches/laksen/riscv_new@39475 -
2018-07-20 10:40:28 +00:00
Jeppe Johansen
ceb38833f2 Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
git-svn-id: branches/laksen/riscv_new@39474 -
2018-07-20 08:21:15 +00:00