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b2427d04ed
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860 Commits

Author SHA1 Message Date
Jonas Maebe
b2427d04ed * ensure that data pools are not inserted right after add/tbb/tbh-based 
jumptable dispatches

git-svn-id: trunk@30027 -
 2015-02-27 20:52:12 +00:00
Jonas Maebe
2ab7f5c35d * moved x86-specific requirements from the generic bsr/bsf code to the 
x86 code generator (register size constraints)

git-svn-id: trunk@29984 -
 2015-02-23 22:57:18 +00:00
Jonas Maebe
d6de2c03cb * generic part of r26050 from the hlcgllvm branch: made tcgvecnode hlcg-safe 
o in particular, add tdef size information to the update_reference*()
     methods, and factored out offset adjustments into its own method
   o also make sure the passed size to update_reference*() corresponds to the
     actual size of the index, as it's no longer guaranteed to be ptruint
     since the previous commit

git-svn-id: trunk@29967 -
 2015-02-23 22:56:00 +00:00
Jonas Maebe
3fe0bd065e * ARM assembler reader: don't check for postfixes beyond the length 
of the opcode

git-svn-id: trunk@29823 -
 2015-02-23 22:47:56 +00:00
florian
9eab90d8c4 * always pass the architecture to the arm assembler 
* encode pld/ldrd in arm.inc using .long, so it causes no errors with older architectures settings of the assembler

git-svn-id: trunk@29780 -
 2015-02-21 21:58:30 +00:00
florian
80cc09e350 o fix wince compilation: 
* apparently, wince (or GNU AS for it) does not support blx imm
  * set FPC_IN_SYSTEM directive, so assembler code in divide.inc is compiled right

git-svn-id: trunk@29779 -
 2015-02-21 21:55:56 +00:00
sergei
9cc0bdd6b9 + Missing part of internal ARM assembler, Mantis #26588. I'm not setting it as default for arm-wince yet, because testing reveals several points in generic code that need adjustments. 
git-svn-id: trunk@29588 -
 2015-01-30 22:45:05 +00:00
sergei
472310d83f * ARM: Fixed interface wrapper generation after r28542 for targets without BX instruction. 
git-svn-id: trunk@29580 -
 2015-01-30 15:00:28 +00:00
florian
d540d56908 * unified internal errors 
git-svn-id: trunk@29280 -
 2014-12-13 11:46:59 +00:00
Jeppe Johansen
3bc1db9612 Fixed breakage in the ARM peephole optimizer indirectly brought to light by r29189. 
git-svn-id: trunk@29191 -
 2014-12-01 14:39:40 +00:00
Jeppe Johansen
d04e988ff1 Make sure optimizer don't generate invalid assembler forms (LDRD and STRD). 
git-svn-id: trunk@29189 -
 2014-11-30 17:34:37 +00:00
florian
5c67fcc43f + change always floating point divisions into multiplications if they are a power of two, 
this is an exact operation so it is always allowed
* change only divisions by normal numbers into multiplications

git-svn-id: trunk@29085 -
 2014-11-16 20:47:38 +00:00
Tomas Hajny
3ee3542744 * boolean constant instead of IFDEFs for detection of microcontroller support 
git-svn-id: trunk@29052 -
 2014-11-10 12:34:59 +00:00
Jeppe Johansen
d3e91bb60c Fixed issue #26965. The peephole optimization didn't move a potential register deallocation to after the ldr instruction causing mov's to be removed. 
git-svn-id: trunk@28977 -
 2014-11-03 18:33:32 +00:00
sergei
a3c439c60f - No longer insert BlockStart markers into asmlists. The presence of these markers disrupts peephole optimizations and require additional checks all over the place, causing various workarounds/hacks (like TAsmList.Create_without_marker) to start building up. 
A more radical approach is to remove them altogether. Tested with i386-win32 (the oldest peephole optimizer), mips-linux (the newest one) and arm-linux (the most complex one) targets. The fallout was limited to two minor issues fixed in r28629 and r28708, respectively.

git-svn-id: trunk@28711 -
 2014-09-22 21:33:50 +00:00
sergei
d37e72dbf9 * ARM: instructions do modify the base register of pre/postindexed references. Report this fact in spilling_get_operation_type_ref and RegModifiedByInstruction functions. 
git-svn-id: trunk@28708 -
 2014-09-22 16:18:16 +00:00
sergei
b08ffa0a87 * ARM: fixed detecting Thumb-style jump tables in insertpcrelativedata() after r28546. 
git-svn-id: trunk@28702 -
 2014-09-21 01:59:25 +00:00
sergei
4a90d7e3de + ARM internal linker: very initial support for Thumb mode, helloworld-class programs compiled with "-Cparmv6m -CIthumb" can now run. 
git-svn-id: trunk@28697 -
 2014-09-19 22:33:37 +00:00
Károly Balogh
1b0a1f4508 ARM: mimic what GNU C does while calling the profiling mcount on ARM 
git-svn-id: trunk@28648 -
 2014-09-13 00:17:10 +00:00
Károly Balogh
739c66291d ARM: first naive attempt to get gprofiling work for arm-linux. (Work-In-Progress, but at least for me it doesn't explode) 
git-svn-id: trunk@28645 -
 2014-09-12 18:51:02 +00:00
florian
3f71b059e5 * improve ldr*/str* handling for arm thumb 
git-svn-id: trunk@28583 -
 2014-09-02 19:37:45 +00:00
florian
2fa7171a45 * generate AND for small set comparisons also when only set vars are involved using the cg class, so it works for arm thumb as well 
git-svn-id: trunk@28569 -
 2014-08-31 20:43:13 +00:00
florian
8a7c16327c * fixes reference handling for arm thumb and ldrh, not perfect yet 
git-svn-id: trunk@28568 -
 2014-08-31 18:00:10 +00:00
florian
81c717fc06 + implemented tthumbcgarm.g_external_wrapper in a way which does not destroy lr 
git-svn-id: trunk@28560 -
 2014-08-31 16:35:01 +00:00
florian
dffdde7d53 * fixes reference handling for arm thumb and ldrb, not perfect yet and other ldr/str types might need similiar fixes 
git-svn-id: trunk@28549 -
 2014-08-31 11:37:17 +00:00
florian
db01c50a4f * fixes jump table generate for arm thumb 
git-svn-id: trunk@28546 -
 2014-08-30 22:13:09 +00:00
florian
836a6e46ca * several issues with interface wrappers for thumb fixed 
git-svn-id: trunk@28542 -
 2014-08-30 20:38:26 +00:00
florian
97fc823e33 * generate AND for small set comparions using the cg class, so it works for arm thumb as well 
git-svn-id: trunk@28540 -
 2014-08-30 18:02:59 +00:00
florian
09728a9ae2 * improved r28534: LDR/STR on thumb do not support registers >r7 as destination/source 
git-svn-id: trunk@28538 -
 2014-08-30 12:13:00 +00:00
Károly Balogh
5a7b1f00cf ARM: Thumb is an ugly mess, but this at least makes fcl-image package to build with -Ooregvar. someone with more clue is welcomed to review and come up with a better patch. 
git-svn-id: trunk@28534 -
 2014-08-29 17:04:48 +00:00
Károly Balogh
09608a1c28 * fix warnings when compiling the compiler with DFA optimizer enabled on ARM 
git-svn-id: trunk@28498 -
 2014-08-20 13:16:58 +00:00
Jonas Maebe
e21d31dc99 * fixed compilation with range checking enabled 
git-svn-id: trunk@28447 -
 2014-08-18 20:06:27 +00:00
Jonas Maebe
5e280b3131 * don't convert movs into (the non-existing) ldrs in do_spill_replace() 
git-svn-id: trunk@28390 -
 2014-08-12 20:14:24 +00:00
masta
96915b3f0c 16bit Thumb is not able to use tst with an immediate value 
r28315 introduced an arm optimization which requires
  tst rX, #imm
to work. This is not available on 16bit thumb, I've disabled that
optimization on thumb for now.

git-svn-id: trunk@28360 -
 2014-08-10 15:30:44 +00:00
masta
7e22bd53b6 Changed ARMs StrLdr2StrMov peephole optimizer look further ahead 
StrLdr2StrMov now uses GetNextInstructionUsingRef to find an instruction
which uses the same Reference. In one of our internal testcases it
speeded up a function by 15% as fpc generated a lot of spilling.

git-svn-id: trunk@28344 -
 2014-08-08 15:31:10 +00:00
masta
bfa85218fa Introduce TCpuAsmOptimizer.GetNextInstructionUsingRef 
It's the counterpart to GetNextInstructionUsingReg and finds the next
instruction to use the same reference. By default it stops searching
when hitting a store instructions to avoid aliasing issues.

git-svn-id: trunk@28343 -
 2014-08-08 15:31:06 +00:00
masta
d1c5f89976 Make Next an Out-parameter in ARMs GetNextInstructionUsingReg 
The input to Next is not used, reflect that properly.

git-svn-id: trunk@28342 -
 2014-08-08 15:31:01 +00:00
masta
b898b169d4 Fixed 0-cmp optimization in tarmaddnode.second_cmp64bit 
Commit r28315 prevented "= 0" compare-optimizations. Should be fixed now.

git-svn-id: trunk@28317 -
 2014-08-06 15:01:24 +00:00
masta
c88fdb6a4a Add minor optimization for int64 < 0 on arm 
This is a very common construct in normal code and also heavily used in
softfpu code.

The ARM-cg will now just test for the MSB of reghi to be set, instead of
a full comparison against constant 0.

git-svn-id: trunk@28315 -
 2014-08-05 21:31:20 +00:00
masta
7a0c79de60 Fix for AndLsl2Lsl in ARM Peephole optimizer 
AndLsl2Lsl assigned the wrong register to the remaining instruction, and
also did not check for the register.

git-svn-id: trunk@28285 -
 2014-07-31 23:09:33 +00:00
masta
85d208fea4 Fix ARM LoadScheduler in case of Pre/PostIndexed addressing 
There was an interference between the load scheduler and then
Str/LdrAdd/Sub2Str/Ldr peephole optimizer.

ldrb r0, [r2]
ldrb r1, [r2, #1]
orr r3, r0, r1
add r2, r2, #2

got changed pre-regalloc to:
ldrb r1, [r2, #1]
ldrb r0, [r2]
orr r3, r0, r1
add r2, r2, #2

and the peephole optimizer collapsed the add into the second ldrd:
ldrb r1, [r2, #1]
ldrb r0, [r2], #2
orr r3, r0, r1

Then the post-peephole optimizer changed that into:
ldrb r0, [r2], #2
ldrb r1, [r2, #1]
orr r3, r0, r1

so r1 got loaded from a modified base-register.

This patch prevents the scheduler from moving an ldr-instruction if it
uses Pre/Post-indexing and the instruction before it uses the
base-register.

git-svn-id: trunk@28284 -
 2014-07-31 19:57:09 +00:00
sergei
e4fea2ebc8 * Dummy implementations of a_bit_scan_reg_reg and g_stackpointer_alloc in tcg, removes the need to override these methods in every descendant code generator solely to avoid "constructing a class with abstract method" warning. 
git-svn-id: trunk@28175 -
 2014-07-06 11:34:04 +00:00
Jeppe Johansen
857a849173 Added an additional check to the MulAdd2MLA optimization. The operands of the multiplication weren't checked. 
git-svn-id: trunk@28071 -
 2014-06-26 06:05:08 +00:00
Jeppe Johansen
a1197460e1 Constrained a number of optimizations and updated reference offsets for ARM Thumb. 
Embedded target can now build with optimizations.

git-svn-id: trunk@28023 -
 2014-06-21 13:26:33 +00:00
Jeppe Johansen
0dc39b5d63 Applied patch from Michael Ring that adds some startup code for some new stm32f0 and stm32f1 controllers, and fixes naming on some LPC ARMv6m controllers. 
git-svn-id: trunk@28009 -
 2014-06-20 06:49:04 +00:00
masta
0cb1a129b3 {ARM} Implement usage of generic division-by-const optimization 
This utilizes the code commited in r27904 to convert a division by const
into a 32x32->64 bit multiplication for ARM.

git-svn-id: trunk@27929 -
 2014-06-10 20:49:18 +00:00
Jeppe Johansen
96b73b0076 Fixed generation of abs calls for thumb and thumb-2 targets. 
git-svn-id: trunk@27926 -
 2014-06-10 17:48:09 +00:00
Károly Balogh
af95876eba arm: an attempt to improve the a_op_const_ref patch in r27881 
git-svn-id: trunk@27882 -
 2014-06-06 20:48:31 +00:00
Károly Balogh
5b262df7d0 arm: have a CPU specific op_const_ref, so the reference doesn't get fixed up both in a_load_reg_ref and a_load_ref_reg 
git-svn-id: trunk@27881 -
 2014-06-06 17:44:45 +00:00
sergei
196436b7e7 * ARM: Test if range check of floating point constants is necessary in the same way as on other targets. This should have been part of r10940 6 years ago... 
git-svn-id: trunk@27630 -
 2014-04-22 06:51:54 +00:00