(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
with the 186+ 'ins' instruction.
git-svn-id: trunk@37446 -
(16-bit and 32-bit), i386 (16-bit and 32-bit) and x86_64 (32-bit and 64-bit).
Known bug: 32-bit addresses with an offset have their offset truncated to its
low 16-bits on i8086
git-svn-id: trunk@37409 -
easily and so that all the values are now available to the compiler
(previously, there were several, which were mapped to the same value and thus
were only used to make x86ins.dat easier to read)
git-svn-id: trunk@37299 -
from cpubase unit to a method in the tcg class. The reason for doing that is
that this is now a standard part of the 16-bit and 8-bit code generators and
moving to the tcg class allows doing extra checks (not done yet, but for
example, in the future, we can keep track of whether there was an extra
register allocated with getintregister and halt with an internalerror in case
GetNextReg() is called for registers, which weren't allocated as a part of a
sequence, therefore catching a certain class of 8-bit and 16-bit code
generator bugs at compile time, instead of generating wrong code).
- removed GetLastReg() from avr's cpubase unit, because it isn't used for
anything. It might be added to the tcg class, in case it's ever needed, but
for now I've left it out.
* GetOffsetReg() and GetOffsetReg64() were also moved to the tcg unit.
git-svn-id: trunk@37180 -
* compinnr.inc include file converted to a unit
* inline number field size stored in ppu increased from byte to longint
* inlines in the parse tree (when written with the -vp option) now printed with
their enum name, instead of number
git-svn-id: trunk@36174 -
and les instructions to also support the lss, lfs and lgs instructions on i386
(won't be generated by the current code generator, but might become useful in
the future, if we start using the fs and gs segment registers as well)
git-svn-id: trunk@35858 -
this removes the limit of 3 Ch_XXX flags per instruction (thus allowing adding
more precise flags, e.g. for tracking only certain bits of the flags register,
etc.) and avoids the ugliness of having the Ch_None filler, which makes
x86ins.dat less readable.
git-svn-id: trunk@35850 -
* AAA and AAS also read flags (AF)
* CMC reads and writes flags (it inverts CF)
* CMPSx and SCASx write flags
* CMPSx, SCASx, LODSx, STOSx, MOVSx read the direction flag
* NOT doesn't affect flags
* REP isn't affected by and doesn't affect flags
* REPE/REPNE/REPZ/REPNZ/REPC/REPNC don't write flags, only read them
* ROL and ROR don't read flags
* SAL doesn't read flags
* SHLD and SHRD don't read flags
git-svn-id: trunk@35849 -
be used (TBD in a future commit) for optimizing x:=-x and x:=not x on CPUs
that support performing these operations directly in memory (such as x86)
git-svn-id: trunk@35749 -
uses less code repetition and allow choosing various methods (some of which
will be implemented later and selected, according to the cpu and optimization
settings (size vs speed))
git-svn-id: trunk@35743 -
