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38 Commits

Author SHA1 Message Date
florian
4f0da5fcc3 + patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799 
+ avxopcodes tests also movbe and pclmulqdq

git-svn-id: trunk@40951 -
 2019-01-20 18:50:12 +00:00
florian
8943c0584e + patch by J. Gareth Moreton to support BMI2 instructions 
+ extended avx test generator with the newly added BMI2 instructions

git-svn-id: trunk@39875 -
 2018-10-07 10:10:19 +00:00
marco
f0042a4719 * vcmppd hardcoded primitives like vcmpeqpd. 
* required increasing maxinfolen to 9 

git-svn-id: trunk@38404 -
 2018-03-03 23:32:54 +00:00
marco
f21a141144 * mantis #32001, add 32 vcmpps variants. 
git-svn-id: trunk@38403 -
 2018-03-03 23:10:03 +00:00
nickysn
ae92973196 + added support for the retw, retnw, retfw, retd, retnd, retfd, retq, retnq and 
retfq x86 instructions. These are variants of the ret instruction with the
  return offset size set explicitly, e.g. retfw is a 16-bit far ret (i.e. pops
  a 16-bit offset and a 16-bit segment), retfd is a 32-bit far ret (pops a
  32-bit offset, followed by a 16-bit segment), etc.

git-svn-id: trunk@37571 -
 2017-11-10 16:53:29 +00:00
nickysn
0fb79946a5 + added support for the parameterized versions of the x86 string instructions 
(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
  and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
  is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
  with the 186+ 'ins' instruction.

git-svn-id: trunk@37446 -
 2017-10-12 00:07:02 +00:00
florian
912e6d129a * fix modification flags for *ROUND* 
git-svn-id: trunk@36280 -
 2017-05-21 11:12:57 +00:00
nickysn
af48d176ec + precise flag information for the ucomiss,ucomisd,vucomiss and vucomisd x86 instructions 
git-svn-id: trunk@36115 -
 2017-05-05 13:41:43 +00:00
nickysn
ff1ee6836d + fix RegReadByInstruction for the x86 MOVSD instruction 
git-svn-id: trunk@35968 -
 2017-04-27 14:42:08 +00:00
nickysn
0c244046a9 * proper register change info for the movs,cmps and scas x86 string instructions 
(movsd still todo, because of the overlap with the sse2 instruction)

git-svn-id: trunk@35929 -
 2017-04-23 21:30:25 +00:00
nickysn
1d34e96064 + added x86 instruction flag Ch_RFLAGScc, indicating instructions that read 
specific bits from the flags register, according to their condition (used by
  Jcc/SETcc/CMOVcc)

git-svn-id: trunk@35907 -
 2017-04-22 22:07:05 +00:00
nickysn
1146b7c12c + added detailed information for individual flag bits use for most x86 
instructions. Not used by the compiler yet, but may allow more
  optimizations in the future.

git-svn-id: trunk@35882 -
 2017-04-21 23:03:33 +00:00
nickysn
869f395a31 + added knowledge to the compiler for the x86 instructions, that don't read 
their input registers, in case both parameters are the same register (e.g.
  xor eax, eax; sub eax, eax; etc.)

git-svn-id: trunk@35861 -
 2017-04-20 15:11:56 +00:00
nickysn
12a1ad66b2 + added the Ch_RDirFlag change attribute to the STOSx instructions (previously 
was missing, due to the 3 attributes per instruction limit)

git-svn-id: trunk@35855 -
 2017-04-19 20:23:24 +00:00
nickysn
9303a8f61a * changed the x86 TInsProp.Ch structure from a 3-element array to a pascal set; 
this removes the limit of 3 Ch_XXX flags per instruction (thus allowing adding
  more precise flags, e.g. for tracking only certain bits of the flags register,
  etc.) and avoids the ugliness of having the Ch_None filler, which makes
  x86ins.dat less readable.

git-svn-id: trunk@35850 -
 2017-04-19 16:48:35 +00:00
nickysn
189e49998c * fixes to the x86 instruction flags tracking attributes: 
* AAA and AAS also read flags (AF)
  * CMC reads and writes flags (it inverts CF)
  * CMPSx and SCASx write flags
  * CMPSx, SCASx, LODSx, STOSx, MOVSx read the direction flag
  * NOT doesn't affect flags
  * REP isn't affected by and doesn't affect flags
  * REPE/REPNE/REPZ/REPNZ/REPC/REPNC don't write flags, only read them
  * ROL and ROR don't read flags
  * SAL doesn't read flags
  * SHLD and SHRD don't read flags

git-svn-id: trunk@35849 -
 2017-04-19 15:42:50 +00:00
florian
56252d59f0 + support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933 
git-svn-id: trunk@34917 -
 2016-11-18 20:19:39 +00:00
florian
a7516dfb50 * fix modification information of VCOMISS and VCOMISD 
git-svn-id: trunk@33874 -
 2016-06-01 19:58:43 +00:00
florian
0c13f3ce3e * fix modification information for vand* 
git-svn-id: trunk@33593 -
 2016-05-01 12:00:25 +00:00
florian
406e3c4ac1 + support xgetbv instruction, resolves issue #29958 
git-svn-id: trunk@33418 -
 2016-04-03 20:53:10 +00:00
florian
8d5cc3dfa4 * (extended and modified) patch by Emelyanov Roman to add suport of RDRAND, RDSEED and TSX instructions set, resolves issue #29893. 
In comparison with the original patch, support for a i386 has been added as well as a test program. 
  Further, a small issue with xbegin has been fixed

git-svn-id: trunk@33375 -
 2016-03-28 19:08:13 +00:00
sergei
0f301b4c57 * Fixed spilling info for vcvt* instructions, part of Mantis #29783. 
git-svn-id: trunk@33208 -
 2016-03-09 16:36:30 +00:00
florian
a3964d9ee0 + support for RDTSCP, resolves issue #28916 
git-svn-id: trunk@32652 -
 2015-12-13 13:28:51 +00:00
florian
99635658ec * corrects change flags for VSQRTSD 
git-svn-id: trunk@30037 -
 2015-02-28 22:42:25 +00:00
florian
d6e4af8279 + applied remaining patches of Torsten Grundke: adds gather instructions of avx2 
git-svn-id: trunk@29745 -
 2015-02-17 21:43:46 +00:00
sergei
dc628b8969 * x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway. 
git-svn-id: trunk@27934 -
 2014-06-11 22:31:40 +00:00
florian
842e027a9f + prove of concept how FMA4 could be supported in inline assembler 
git-svn-id: trunk@27214 -
 2014-03-20 21:25:38 +00:00
florian
a79be2b05c + support for FMA instructions in inline assembler 
+ extended avx test code with FMA

git-svn-id: trunk@27209 -
 2014-03-20 20:06:56 +00:00
florian
aa107b914c * merged avx2 branch, developed by Torsten Grundke 
git-svn-id: trunk@27200 -
 2014-03-20 12:03:52 +00:00
florian
13cb468a8e * fixed modification information for some avx instructions 
git-svn-id: trunk@26840 -
 2014-02-22 15:52:33 +00:00
florian
be0a29da95 * fix modification information for bmi instructions 
git-svn-id: trunk@26738 -
 2014-02-08 21:38:21 +00:00
Jonas Maebe
a1eb9a0f99 * fixed spilling of CMOVcc instruction: it "reads" operand two (in the sense 
that the value of operand two is used/kept in case the condition is false)
    (fixes mantis #25672)

git-svn-id: trunk@26674 -
 2014-02-05 00:27:21 +00:00
florian
8989a40b4f * more flags to mark changes fixed 
git-svn-id: trunk@26626 -
 2014-01-30 17:34:28 +00:00
florian
2ec5a649d7 * set Ch_* for more operations 
* Ch_* flags for VMOVSD and VMOVSS are now set for the 2 operand variants

git-svn-id: trunk@26586 -
 2014-01-26 12:37:50 +00:00
florian
7028210817 + tzcnt assembler instruction 
git-svn-id: trunk@26506 -
 2014-01-18 12:11:50 +00:00
nickysn
f6e846c574 + added the NEC V20/V30 instructions 
git-svn-id: trunk@25750 -
 2013-10-11 21:27:56 +00:00
nickysn
4929bc5694 * regenerated the i8086 ins files 
git-svn-id: trunk@25603 -
 2013-09-28 21:10:23 +00:00
nickysn
107a6f6552 * i8086 versions of i386*.inc and r386*.inc renamed to i8086*.inc and r8086*.inc 
git-svn-id: branches/i8086@24232 -
 2013-04-12 12:06:28 +00:00