Commit Graph

201 Commits

Author SHA1 Message Date
florian
316f2429f0 * do not omit location_force_reg on second operand of sar/ro* if
it is used to adapt the size of the operand

git-svn-id: trunk@48855 -
2021-03-01 20:21:42 +00:00
florian
01178532e5 * sar*/ro* do not call location_force_reg if not needed
git-svn-id: trunk@48844 -
2021-02-28 22:11:05 +00:00
yury
64c586b86d * Removed/ifdefed lots of unused variables.
git-svn-id: trunk@48384 -
2021-01-24 12:24:01 +00:00
florian
6e4997265c + min/max intrinsics for internal use by the compiler
git-svn-id: trunk@47692 -
2020-12-05 22:00:58 +00:00
florian
637976e83f * patch by Marģers to unify internal error numbers, resolves #37888
git-svn-id: trunk@47103 -
2020-10-13 19:59:01 +00:00
nickysn
0f6ab0de17 * handle LOC_(C)SUBSETREG/REF in second_NegNot_assign
* changed the way OP_NEG and OP_NOT are handled in op_reg_ref, in order to be
  consistent with op_reg_reg
* introduced op_reg,op_ref,op_subsetreg,op_subsetref and op_loc for the unary
  operations only (OP_NEG,OP_NOT)

git-svn-id: trunk@45302 -
2020-05-07 02:43:02 +00:00
nickysn
5aaf863d56 * only call cg64.a_XXX_loc for LOC_(C)REFERENCE and LOC_(C)REGISTER locations in
tcginlinenode.second_AndOrXorShiftRot_assign

git-svn-id: trunk@45301 -
2020-05-06 21:24:19 +00:00
florian
cfe2d94b25 * fix LLVM after r45177
git-svn-id: trunk@45198 -
2020-04-30 19:42:03 +00:00
florian
9e0337f248 * do not use an extra register in tcginlinenode.second_IncDec if not needed
git-svn-id: trunk@45177 -
2020-04-29 20:01:53 +00:00
florian
6c71fd461d * avoid internalerror for dec/inc(...,v) with v>high(int64), resolves #35298
git-svn-id: trunk@44031 -
2020-01-24 21:39:07 +00:00
florian
70a836c4a2 * first part of merging parts of Jeppe's intrinsics patch, mainly r31135
is merged by this commit with a lot of adaptions

git-svn-id: trunk@43949 -
2020-01-14 21:52:39 +00:00
florian
f7a052f884 + inline high(<dyn. array>), resolves #28536
git-svn-id: trunk@43808 -
2019-12-28 21:38:38 +00:00
Jonas Maebe
04d295f186 * first step towards supporting 32 bit targets with the LLVM code generator:
use the generic code in more cases when cpuhighleveltarget is defined

git-svn-id: trunk@41133 -
2019-01-29 21:39:09 +00:00
Jonas Maebe
122d0d36d6 + volatile() expression that marks an expression as volatile
* disable matching volatile references in the assembler optimisers, so they
    can't be removed (more conservative than needed, but better than removing
    too many)
   o the CSE optimiser will ignore them by default, because they're an unknown
     inline node for it
  * also removed no longer used fpc_in_move_x and fpc_in_fillchar_x inline node
    identifiers from rtl/inc/innr.inc, and placed fpc_in_unaligned_x at the
    right place

git-svn-id: trunk@40465 -
2018-12-04 19:53:20 +00:00
Károly Balogh
6629e72d79 m68k: reinstate the inc/dec tempregister type hack again in an isolated way (it was removed in r40385, as it was breaking llvm target)
git-svn-id: trunk@40453 -
2018-12-02 18:54:04 +00:00
Jonas Maebe
026d06cffb - reverted r39188, as this hack removes the type correctness of the
instructions, which breaks the llvm code generator. Put such hacks
    in CPU-specific overrides

git-svn-id: trunk@40385 -
2018-11-28 19:23:31 +00:00
Károly Balogh
bbbaa39d79 ncginl: another approach to fix the same issue #39184 supposed to address. keep left.resultdef, but try to make the target def always ordinal of an equal size, so it ends up in a data register on m68k
git-svn-id: trunk@39188 -
2018-06-07 06:43:02 +00:00
Károly Balogh
3286623c3c ncginl: revert the previous commit, it seems to cause some issues on other CPUs
git-svn-id: trunk@39186 -
2018-06-07 06:21:46 +00:00
Károly Balogh
42efddc481 ncginl: in inc/dec, do not use left.resultdef as the dest to force a register location, because if left is a pointer, then an ordinal value might get forced into an address register on m68k, which results in a lot of unnecessary register shuffling to complete the operation
git-svn-id: trunk@39184 -
2018-06-07 06:04:19 +00:00
Jonas Maebe
4686f61002 * keep track of the temp position separately from the offset in references,
so that they can still be freed after the reference has been changed
    (e.g. in case of array indexing or record field accesses) (mantis #33628)

git-svn-id: trunk@38814 -
2018-04-22 17:03:16 +00:00
florian
4752b0ef96 + tinlinenode calls cpu specific routines for unknown inline numbers
git-svn-id: trunk@37543 -
2017-11-01 16:33:32 +00:00
florian
8eec29b139 + enable support for a processor specific frac function
* implemented inlined frac support for CPUs with SSE4.1+

git-svn-id: trunk@36281 -
2017-05-21 11:12:59 +00:00
nickysn
efc5e339d0 * use an enum instead of integer constants to represent inline numbers
* compinnr.inc include file converted to a unit
* inline number field size stored in ppu increased from byte to longint
* inlines in the parse tree (when written with the -vp option) now printed with
  their enum name, instead of number

git-svn-id: trunk@36174 -
2017-05-10 14:41:43 +00:00
florian
b1dff29cbf * removed unused units
git-svn-id: trunk@36165 -
2017-05-09 19:53:14 +00:00
nickysn
d8ec0eff8e + implemented inline code generation for 64-bit sar (the SarInt64 intrinsic) on
less-than-64-bit CPUs that have a 64-bit OP_SHR/OP_SHL/OP_SAR implementation
  in their cg64 backend code generator. This is enabled only for i386 for now.

git-svn-id: trunk@36022 -
2017-04-30 16:06:34 +00:00
nickysn
ec11864272 * use a native sized int register for the shift count in in_sar_assign_x_y,
in_shl_assign_x_y,in_shr_assign_x_y,in_rol_assign_x_y,in_ror_assign_x_y

git-svn-id: trunk@35857 -
2017-04-20 12:38:54 +00:00
nickysn
599b9e73de * determine correctly whether operand size is 32 or 64 bits for
sar/shl/shr/rol/ror in tcginlinenode.second_AndOrXorShiftRot_assign

git-svn-id: trunk@35783 -
2017-04-12 13:36:42 +00:00
nickysn
f514657e45 + implemented the sar/shl/shr/rol/ror inline modify-in-place nodes; the actual
optimization of "i:=i shl/shr k", etc statements is not performed yet

git-svn-id: trunk@35780 -
2017-04-12 00:41:15 +00:00
nickysn
c6680a32d7 * also support LOC_CREGISTER and LOC_CREFERENCE in in_not_assign_x and in_neg_assign_x
git-svn-id: trunk@35751 -
2017-04-07 21:33:56 +00:00
nickysn
6b43705437 * fixed compiler internal error when the in_not_assign_x/in_neg_assign_x are
applied to a LOC_REGISTER variable

git-svn-id: trunk@35750 -
2017-04-07 19:16:00 +00:00
nickysn
256dc546ac + implemented the in_neg_assign_x and in_not_assign_x inline nodes, which will
be used (TBD in a future commit) for optimizing x:=-x and x:=not x on CPUs
  that support performing these operations directly in memory (such as x86)

git-svn-id: trunk@35749 -
2017-04-07 16:02:40 +00:00
florian
4504648ec1 * initialize maskvalue to fix compilation with -O3+
git-svn-id: trunk@35707 -
2017-04-01 19:03:35 +00:00
nickysn
f19ebe2acf * fixed compiler internal error in the in_[and/or/xor]_assign_x_y inline nodes
when their second parameter is a large 64-bit unsigned constant

git-svn-id: trunk@35684 -
2017-03-29 14:55:07 +00:00
nickysn
fc59649a98 + added inline nodes for handling and/or/xor in place (i.e. x:=x op y, where
op=and/or/xor). They generate more optimal code on certain architectures
  (including x86). The new inline nodes aren't generated by the compiler yet,
  but will be used in the future, at certain optimization levels, whenever the
  pattern x:=x op y is detected by the compiler.

git-svn-id: trunk@35666 -
2017-03-26 23:16:53 +00:00
Jonas Maebe
a25ebbba3e + added volatility information to all memory references
o separate information for reading and writing, because e.g. in a
     try-block, only the writes to local variables and parameters are
     volatile (they have to be committed immediately in case the next
     instruction causes an exception)
   o for now, only references to absolute memory addresses are marked
     as volatile
   o the volatily information is (should be) properly maintained throughout
     all code generators for all archictures with this patch
   o no optimizers or other compiler infrastructure uses the volatility
     information yet
   o this functionality is not (yet) exposed at the language level, it
     is only for internal code generator use right now

git-svn-id: trunk@34996 -
2016-11-27 18:17:37 +00:00
Károly Balogh
c3e68d6b2d inline: implemented the second pass stub calls for inl_int_real nodes
git-svn-id: trunk@34992 -
2016-11-27 17:48:36 +00:00
Jonas Maebe
de465e056b * set the alignment resulting from an aligned() call to the actual natural
alignment of the resultdef rather than to 0 (required for llvm, and
    cleaner since then the code generator knows the actual alignment)

git-svn-id: trunk@34296 -
2016-08-13 14:47:26 +00:00
Jonas Maebe
8917633199 * implement sizeof/typeof completely at the node level, based on
loadvmtaddr and vmt_def
   o give an error when trying to use sizeof on a class/object when
     targeting the JVM (can't get/load the data size there)

git-svn-id: trunk@32764 -
2015-12-27 14:22:06 +00:00
Jonas Maebe
da696057ab * converted register_maybe_adjust_setbase() to the high level code generator
git-svn-id: trunk@32591 -
2015-12-05 18:03:37 +00:00
Jonas Maebe
67b8aceaee * synchronized with privatetrunk till r30095
git-svn-id: branches/hlcgllvm@30101 -
2015-03-05 20:32:15 +00:00
Jonas Maebe
2ab7f5c35d * moved x86-specific requirements from the generic bsr/bsf code to the
x86 code generator (register size constraints)

git-svn-id: trunk@29984 -
2015-02-23 22:57:18 +00:00
Jonas Maebe
5e339e89e4 * source can also be a LOC_CREGISTER for bsr/bsf
git-svn-id: trunk@29980 -
2015-02-23 22:57:05 +00:00
Jonas Maebe
e8026ad8d3 * fixed the resultdef of length() intrinsic: it's ossinttype rather than
sinttype (they're the same on most platforms, except on 8 bit ones where
    ossinttype is still 16 bit)
  * simplified and documented second_length(), and fixed some (harmless)
    errors in the used tcgsize for the resultdef (it had to be OS_SINT
    rather than OS_INT -- now it's just def_cgsize(resultdef) so it's
    always correct)

git-svn-id: branches/hlcgllvm@28387 -
2014-08-12 18:59:13 +00:00
nickysn
214eaebf99 * fixed length(ansistring/widestring/dynarray) in i8086 far data memory models
git-svn-id: trunk@27673 -
2014-04-27 02:26:35 +00:00
florian
d88d644925 + support for FMA intrinsic: if there is no hardware support, the compiler throws an error.
Currently it is implemented only for x86-CPUs supporting the FMA extension. While it would
  be possible to implement it in software or simulate fma(<single>,<single>,<single>) using
  double operations, it makes no sense in my opinion to do so.

git-svn-id: trunk@27564 -
2014-04-13 19:21:54 +00:00
nickysn
81875346cf * fixed tcginlinenode.second_SizeOfTypeOf for i8086 far data memory models by
using the high level code generator for all operations, that involve pointers

git-svn-id: trunk@27310 -
2014-03-28 00:07:39 +00:00
nickysn
6e9083aa84 * fixed inc/dec with constant truncating the high parts of the constant on
16-bit and 8-bit CPUs

git-svn-id: trunk@26908 -
2014-03-01 10:33:14 +00:00
nickysn
5e0359d389 * 16/8-bit ALU fix for 64-bit pred/succ after r26580
git-svn-id: trunk@26590 -
2014-01-26 15:44:58 +00:00
florian
cb8100bccf * do not reuse registers in prec/succ
git-svn-id: trunk@26580 -
2014-01-25 09:40:48 +00:00
florian
4d5119bf1c * fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables
git-svn-id: trunk@26161 -
2013-12-01 17:02:08 +00:00