florian cafaa9f5b8 + RiscV: handle rol(w) in the assembler optimizer		2025-03-23 23:04:17 +01:00
..
aasmcpu.pas	* RiscV: handle more instructions in taicpu.spilling_get_operation_type	2025-02-20 23:05:52 +01:00
agrvgas.pas	+ RiscV: rv32gcb	2025-02-22 21:57:52 +01:00
aoptcpurv.pas	+ RiscV: handle rol(w) in the assembler optimizer	2025-03-23 23:04:17 +01:00
cgrv.pas	+ a_bit_scan_reg_reg gets a flag if src cannot be zero: this simplifies the generated code	2025-02-08 14:27:48 +01:00
cpubase.pas	* remove accidently committed debug statement	2025-01-12 11:32:34 +01:00
hlcgrv.pas
itcpugas.pas	+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0	2025-01-11 21:03:54 +01:00
nrvadd.pas	+ RiscV: support ZMMUL extension	2025-01-26 14:43:57 +01:00
nrvcnv.pas
nrvcon.pas	* RiscV: check for cpu capabilities before using fmv for loading zero	2025-01-12 18:30:32 +01:00
nrvinl.pas	+ min/max optimization support for RiscV	2025-01-06 15:21:18 +01:00
nrvmat.pas	+ RiscV: make use of the fneg.* instruction	2025-01-09 22:25:26 +01:00
nrvset.pas	+ RiscV64: apply OptPass1OP also to addiw	2024-11-13 22:56:13 +01:00
nrvutil.pas	* fix typo	2025-02-21 22:47:44 +01:00
pararv.pas	* RiscV: push_addr_param unified	2024-12-26 16:49:43 +01:00
rarv.pas
rarvgas.pas
rgcpu.pas
rvreg.dat	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00