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29 Commits

Author SHA1 Message Date
florian
065ddfd8d4 + RiscV: ROL/ROR code generation support 2025-03-25 22:40:26 +01:00
florian
b2f6214b33 + a_bit_scan_reg_reg gets a flag if src cannot be zero: this simplifies the generated code 2025-02-08 14:27:48 +01:00
florian
95c2a5a2d7 + RiscV: support ZMMUL extension 2025-01-26 14:43:57 +01:00
florian
1202b2612f + RiscV: make use of the fl* rd,symbol,rd pseudoinstruction 2025-01-11 14:22:01 +01:00
florian
a370b6ff1d * set is_jmp 2025-01-07 22:51:16 +01:00
florian
64ba751ef1 * make use of LA pseudo-instruction 2024-12-25 18:35:46 +01:00
florian
0b49fba637 + more RiscV extensions 
* make use of F and D extension flags
 2024-11-17 15:05:35 +01:00
florian
1d629270ca * RiscV64: fix abs(<longint>) 2024-10-14 21:10:10 +02:00
florian
081af9a892 * overleft cosmetics 2024-08-13 22:54:19 +02:00
florian
a71cc71585 + function needs_check_for_fpu_exceptions to unify fpu exception handling 2024-02-13 17:42:21 +01:00
florian
e66378ee59 * RiscV: generate mret only for FreeRTOS and Embedded 2022-07-20 22:16:19 +02:00
Jeppe
f5cf8956c5 riscv: Merge stack code, fix interrupted code 
- Stack pointer is kept below register save area. This ensures that
registers are not overwritten by interrupt handlers.
- RV32 and 64 code is merged to base class.
 2022-07-02 15:07:42 +02:00
pierre
9775a13e02 Rough fix for riscv32 failure 
git-svn-id: trunk@48959 -
 2021-03-14 09:10:29 +00:00
florian
e047e7db91 + RiscV: initial support of pic generation 
git-svn-id: trunk@48947 -
 2021-03-13 16:18:00 +00:00
florian
c15bb07bf6 * do not generate mul instructions if the mul extension is not available 
git-svn-id: trunk@48883 -
 2021-03-06 14:23:54 +00:00
pierre
d4c9e1f260 Replace outdated cgop2string function by tcgsize2str function from cgbase unit to fix EXTDEBUG cycle on powerpc64le-linux 
git-svn-id: trunk@46689 -
 2020-08-25 13:29:16 +00:00
pierre
92b0ea7d02 Add explicit smallint typecast to first marameter of SarSmallint call to avoid range check errors 
git-svn-id: trunk@43613 -
 2019-11-29 23:26:45 +00:00
florian
b3ed34592f + software handling of exceptions on arm 
* reworked software handling of exceptions so they can be check lazily

git-svn-id: trunk@42525 -
 2019-07-28 21:06:36 +00:00
pierre
aa89182bf5 Fix compilation with -dEXTDEBUG 
git-svn-id: trunk@39923 -
 2018-10-13 11:34:53 +00:00
Jeppe Johansen
d33b520690 Clean up peephole optimization code. 
Add hardfloat ABI option for RiscV. Still needs proper implementation though.
Add CG support for profiling.

git-svn-id: branches/laksen/riscv_new@39798 -
 2018-09-24 17:15:22 +00:00
Jeppe Johansen
74a7963d58 Redo overflow checking code. 
Fix shift operators in case of unsigned subreg operations. There should be no sign extension here.
Add some unittest implementations that test stack execution and writing to readonly constants.

git-svn-id: branches/laksen/riscv_new@39762 -
 2018-09-16 18:37:59 +00:00
florian
4f052e4f90 o fix several issues with floating point exceptions 
+ mask underflow and precision on startup
  + check for floating point exceptions after inlined float routine helpers
  - do not check for floating point exceptions after floating point moves 

git-svn-id: branches/laksen/riscv_new@39645 -
 2018-08-19 15:26:00 +00:00
florian
999cbd94b8 + support to generate software based floating point exception checking 
(enabled by -CE)

git-svn-id: branches/laksen/riscv_new@39639 -
 2018-08-19 10:56:47 +00:00
Jeppe Johansen
a8c82856b1 Fixed missing maybeadjust calls after not operation. 
git-svn-id: branches/laksen/riscv_new@39493 -
 2018-07-23 10:20:32 +00:00
Jeppe Johansen
b98eb3daa9 Changed order in stack unravelling RTL code, to match the most common cases. 
Fixed unsigned conditions for branch conditions.
Added some additional const loading cases.
Changed the temporary register used during calls because it could otherwise clash with the argument passing registers.

git-svn-id: branches/laksen/riscv_new@39492 -
 2018-07-23 01:11:31 +00:00
Jeppe Johansen
c6b27bc225 Fix shift operations on 32bit operands. 
git-svn-id: branches/laksen/riscv_new@39489 -
 2018-07-22 19:25:46 +00:00
Jeppe Johansen
2499129ba5 Pass aggregates larger than 2*XLEN as a reference. 
Fix load_reg_reg and make it do proper type conversions.
Added maybeadjust to tcgrv.

git-svn-id: branches/laksen/riscv_new@39485 -
 2018-07-22 14:15:29 +00:00
Jeppe Johansen
054bf32f1f Add RV64GC cpu type. 
Fix float loading.
Fix a number of small issues with wrong operand sizes.
Fixed concatcopy code generation.
Align jump table for case statements.

git-svn-id: branches/laksen/riscv_new@39481 -
 2018-07-21 22:34:42 +00:00
Jeppe Johansen
ceb38833f2 Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk. 
git-svn-id: branches/laksen/riscv_new@39474 -
 2018-07-20 08:21:15 +00:00