florian
831a46eb2f
+ more sext.b usage
2025-02-25 22:50:14 +01:00
florian
e219b24aec
* RiscV64: make use of sext.h instruction
2025-02-23 23:11:01 +01:00
florian
d842d822ff
* RiscV64: make use of zext.w instruction if available
2025-02-19 22:44:03 +01:00
florian
5bb4049737
* remove accidently committed debug statement
2025-01-12 11:32:34 +01:00
florian
49aa141703
* major parts of the RiscV paramgr unified, improves code generation and less failures in RiscV32 regression tests
2024-12-22 22:37:16 +01:00
florian
1d629270ca
* RiscV64: fix abs(<longint>)
2024-10-14 21:10:10 +02:00
florian
fdae200281
* RiscV64: don't use addiw for OS_32 to OS_32 type conversions obviously
2024-09-26 21:48:53 +02:00
florian
d247c30965
* RiscV64: better code generation to clear upper 32 bit of a register
2024-09-23 22:28:09 +02:00
florian
159d97e864
* Risc-V: make use of sext.h instruction if available
2024-08-15 21:53:04 +02:00
florian
a53eb8b230
+ Risc-V: make use of zext.h if available
2024-08-14 22:37:26 +02:00
florian
39f7172ee8
* do no generated debug comment in assembler output of RiscV if not requested
2024-05-25 20:16:42 +02:00
florian
f49da05633
* unified g_concatcopy_move
2024-05-15 22:52:24 +02:00
Jeppe
f5cf8956c5
riscv: Merge stack code, fix interrupted code
...
- Stack pointer is kept below register save area. This ensures that
registers are not overwritten by interrupt handlers.
- RV32 and 64 code is merged to base class.
2022-07-02 15:07:42 +02:00
florian
ca29df1aa9
* Risc-V: return with mret from interrupt handlers, resolves #39737
2022-05-27 23:33:20 +02:00
florian
b9affc3406
* RiscV64: type conversion to 8 bit improved
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git-svn-id: trunk@49015 -
2021-03-19 17:39:52 +00:00
Jonas Maebe
1e3f72403e
* renamed getintparaloc to getcgtempparaloc
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o it can be used for more than integer parameters
git-svn-id: trunk@43781 -
2019-12-24 22:12:25 +00:00
pierre
92b0ea7d02
Add explicit smallint typecast to first marameter of SarSmallint call to avoid range check errors
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git-svn-id: trunk@43613 -
2019-11-29 23:26:45 +00:00
Jonas Maebe
281b3ad276
* fix case completeness and unreachable code warnings in compiler that would
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be introduced by the next commit
git-svn-id: trunk@42046 -
2019-05-12 14:29:03 +00:00
Jeppe Johansen
2b78a8fd3d
- Add support for .option directive in riscv assembler.
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- Use addiw when adjusting U32 to S32
git-svn-id: trunk@41870 -
2019-04-14 20:51:29 +00:00
pierre
53a27fe7b3
Disable range check in m68k:tiscv32 and riscv64 cgcpu units
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git-svn-id: trunk@40319 -
2018-11-15 16:58:40 +00:00
Jeppe Johansen
74a7963d58
Redo overflow checking code.
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Fix shift operators in case of unsigned subreg operations. There should be no sign extension here.
Add some unittest implementations that test stack execution and writing to readonly constants.
git-svn-id: branches/laksen/riscv_new@39762 -
2018-09-16 18:37:59 +00:00
Jeppe Johansen
1f68caaf82
Removed reuse of src and dest registers in g_concatcopy as that
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could modify registers used for other stuff(ex. framepointer).
git-svn-id: branches/laksen/riscv_new@39717 -
2018-09-09 14:02:54 +00:00
Jeppe Johansen
90d5f5e760
Added library search paths.
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Removed GP and TP from allocatable registers for now. GP should not be overwritten.
Ported dllprt0.as
Fixed register usage in cprt0.as
git-svn-id: branches/laksen/riscv_new@39522 -
2018-07-29 13:08:15 +00:00
Jeppe Johansen
27ab039366
Fixed _fini and _init references in cprt0.as
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Add RiscV to fcl-res and fpcres.
Check that constant is a valid imm12 when doing overflow checking.
git-svn-id: branches/laksen/riscv_new@39494 -
2018-07-23 11:40:55 +00:00
Jeppe Johansen
b98eb3daa9
Changed order in stack unravelling RTL code, to match the most common cases.
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Fixed unsigned conditions for branch conditions.
Added some additional const loading cases.
Changed the temporary register used during calls because it could otherwise clash with the argument passing registers.
git-svn-id: branches/laksen/riscv_new@39492 -
2018-07-23 01:11:31 +00:00
Jeppe Johansen
2499129ba5
Pass aggregates larger than 2*XLEN as a reference.
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Fix load_reg_reg and make it do proper type conversions.
Added maybeadjust to tcgrv.
git-svn-id: branches/laksen/riscv_new@39485 -
2018-07-22 14:15:29 +00:00
florian
9776ea2afe
* SLTIU -> SLTU
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git-svn-id: branches/laksen/riscv_new@39484 -
2018-07-22 13:55:53 +00:00
florian
65a415c13e
* fix assembling with official binutils
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* fix compilation on 32 bit hosts
+ compile with -Sew
git-svn-id: branches/laksen/riscv_new@39482 -
2018-07-22 13:10:24 +00:00
Jeppe Johansen
054bf32f1f
Add RV64GC cpu type.
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Fix float loading.
Fix a number of small issues with wrong operand sizes.
Fixed concatcopy code generation.
Align jump table for case statements.
git-svn-id: branches/laksen/riscv_new@39481 -
2018-07-21 22:34:42 +00:00
Jeppe Johansen
768fc2ea4b
Added overflow checking in for add instructions.
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git-svn-id: branches/laksen/riscv_new@39479 -
2018-07-20 15:34:22 +00:00
Jeppe Johansen
ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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git-svn-id: branches/laksen/riscv_new@39474 -
2018-07-20 08:21:15 +00:00
