+ a_load_const_ref: use CLR and MOV3Q if possible.
* a_cmp_reg_reg_label: force size to 32 bits for ISA_A and ISA_A+ targets.
+ support for stack frames larger than 32767 bytes.
git-svn-id: trunk@28298 -
* Parameter offsets are now calculated similar to other targets, target_info,first_parm_offset is applied only to callee side, while at caller side offsets start from 0.
* For cdecl procedures, parameters are removed by caller, for the rest it's still done by callee (resembles i386 target, except there is no 'register' calling convention).
git-svn-id: trunk@28185 -
* records are passed by value
* records with size of 1,2 or 4 are returned in registers
* parameters with size<4 are justified on the stack according to big-endian target
Now everything except floating-point parameters is compatible with C code compiled with "-malign-int -mrtd".
Compatibility with "-mno-align-int" is achievable by changing target_info.maxCrecordalign to 2, but doings so causes a lot more troubles because RTL (incorrectly) assumes that records declared with {$PACKRECORDS C} are aligned to pointer size.
+ Reuse parameter locations. Since everything is passed on stack, it reduces code size quite a bit.
- tm68kparamanager.getintparaloc removed, generic implementation has been tested and works as expected.
git-svn-id: trunk@28083 -
m68k/cgcpu.pas, tcg68k:
+ override g_adjust_self_value as we don't do register allocation for the wrapper we need to adjust the Self value using the scratch registers (could be improved however) and we also can not use the offset that the original procedure in tcg uses
* fix g_intf_wrapper by using the correct operations and loading the correct (virtual) method offset
git-svn-id: trunk@25728 -
m68k/cgcpu.pas, tcg68k:
- remove g_save_registers and g_restore_registers which DID NOT CALL inherited!
- also remove commented methods g_save_all_registers & g_restore_all_registers
git-svn-id: trunk@25715 -
- removed the ancient DEBUG_CHARLIE silliness... :)
- moved some repeated code patterns into separate functions
- rewrote most of of tcg68k.a_op_const_reg and tcg68k.a_op_reg_reg
- smarter code generation in tcg68k.a_cmp_const_reg_label
- added support for MULU/MULS on Coldfire in a case which is often used by the CG to index arrays to be used instead of the RTL helpers, this results in a *HUGE* speedup in tw5086 for example
git-svn-id: trunk@25702 -
m68k/cgcpu.pas, tcg68k.g_proc_exit:
* use A0 (which is a volatile register) instead of A3 (which is not) to restore the stack pointer
git-svn-id: trunk@25663 -
m68k/cgcpu.pas, tcg68k:
* a_load_ref_cgpara: use pashsize instead of paraloc^.size as the latter could be OS_NO and thus a "move" instead of a "move.x" will be generated resulting in a word move when a long or byte move might have been necessary
* a_load_reg_ref: use the smallest size when moving the value to a reference
* a_load_ref_ref: when the size is different always use a temporary register for a ref to ref move
* a_load_ref_ref: when doing a fixed move for Coldfire use the correct ref (that's another embarrasing error...) and size (fixes usage of String[Index] for a const array parameter)
* a_load_ref_reg: use the smallest size when moving the value from a reference
* g_concatcopy: don't use source.alignment as that doesn't contain the correct value and also load the value into the temp register using the correct size (fixes passing of small values as parameters, like chars)
git-svn-id: trunk@25624 -
m68k/cgcpu.pas, tcg68k.g_flags2reg:
* don't sign extend the flag value which was stored to the register, but instead do a "AND 1" on it to reduce it to 1 bit; afterall Booleans in Pascal are either 0 or 1 and not 0 or $FF
+ added test
git-svn-id: trunk@25598 -
Therefor the cpu type (-Cp...) "coldfire" was split up into "isaa", "isaa+", "isab" and "isac". The Linux RTL can currently compiled for "68020", "isab" and "isac". For the other three Bcc.L must be handled differently (only Bcc.B/W supported) and for "68000" also EXT.L needs to be handled differently.
fpcdefs.inc:
+ define CPUCAPABILITIES if capabilities can be set for a certain CPU type (currently ARM, AVR and M68k)
options.pas:
* check for CPUCAPABILITIES instead of specific CPUs
assemble.pas:
- the handling of the CPU type is already done in m68k/ag68kgas.pas, Tm68kGNUAssembler.MakeCmdLine (and thereby already using the gascputypestr array!)
m68k/cpuinfo.pas:
- tcputype: remove "cpu_coldfire"
+ tcputype: add "cpu_isa_a", "cpu_isa_a_p", "cpu_isa_b" and "cpu_isa_c"
+ add "cpu_coldfire" constant which contains all Coldfire specific cpu types
* adjust "cputypestr" and "gascputypestr"
+ add tcpuflags and cpu_capabilities (DBRA restriction was checked with CPUCOLDFIRE, CAS/TAS will be needed for atomic operations and BRAL restriction was discovered during testing of new cpu types)
m68k/cgcpu.pas:
* adjust checks for "cpu_coldfire"
m68k/n68kadd.pas:
* don't use a BRA.L if it is not supported, but (at least for now) a BRA.W
aggas.pas:
* adjusted check for Coldfire
git-svn-id: trunk@25457 -
m68k/cgcpu.pas, tcg68k:
+ overload "a_loadfpu_ref_cgpara" and use the 64-bit code generator to pass Doubles if they are located in references
Fixes around nearly 100 tests.
git-svn-id: trunk@23597 -
m68k/aasmcpu.pas, taicpu.spilling_get_operation_type:
* add all Sxx instructions as "operand_write" instructions
m68k/n68kadd.pas, t68kaddnode.getresflags:
* use the correct operation in case of swapped nodes
m68k/cgcpu.pas, tcg68k.g_flags2reg:
- don't move a 0 to the register, because this will CLR it and thus the flags won't be valid anymore...
- NEG would have been the wrong operation (NOT would have been correct), but it isn't needed anyway...
* simplify the method by handling the address register case only when necessary
git-svn-id: trunk@23383 -
use the correct flag for the copy loop: we jump back to the copy code as long as the value is positive aka BPL instead of BMI
This fixes around 30 tests (it fixes a quite bit more, but now some other tests seem to be broken...)
git-svn-id: trunk@23373 -
that the type of the parameters can be determined automatically
o added compilerproc declarations for all helpers called in the compiler
via their assembler name, so we can look up the corresponding procdef
git-svn-id: trunk@23325 -
+ a_op64_reg_reg: add support for "NEG" and "NOT" of 64-bit values
+ a_op64_const_reg: make sure that we know whether a NEG or NOT with a constant is performed
git-svn-id: trunk@22930 -
* in case of copying from the parameter location to the local location we need to use the alignment size for the source as byte/word values are passed as LongInts (this is how the ABI is specified)
git-svn-id: trunk@22924 -
+ add methods "call_rtl_mul_const_reg" and "call_rtl_mul_reg_reg" which can call the RTL helpers "fpc_mul_longint" and "fpc_mul_longword" (based on AVR code)
* use the new call methods for the RTL to correctly pass the parameters (on the stack, not in registers...)
git-svn-id: trunk@22892 -
* don't do a sign_extend, but use the correct move size to copy the const; this fixes the setting of the line ending style inside of "Assign"
=> output of strings does now work correctly!
git-svn-id: trunk@22890 -
(of which the names had changed from FPC_MUL_LONGWORD->FPC_MUL_DWORD and FPC_MOD_CARDINAL->
FPC_MOD_DWORD).
Also disable the usage of FPU opcodes for Coldfire.
git-svn-id: trunk@22739 -
M68000 CPUs they are nevertheless more restricted in some cases, so these need to be
handled explicitely (especially if symbols are involved).
git-svn-id: trunk@22738 -
* generate special return code for non-68020 CPU which don't support RTD instruction (based on
out code a few lines further down)
git-svn-id: trunk@22736 -
leave "and" and "or" as "and" and "or" as according to the assembly language reference the
assembler should automatically choose the correct instruction (though Coldfire still should
be tested for ORI/ANDI to CCR
git-svn-id: trunk@22733 -
* use andi/ori for constant values
* use a scratch register if target is an address register (there seems to exist an omnious
anda/ora instruction though, but GNU as doesn't seem to handle it... maybe I haven't set
the CPU type correctly, so I'll need to investigate this so we can hopefully remove the
need for a scratch register for certain CPU types ;) )
git-svn-id: trunk@22732 -
* $CPU/cgcpu.pas: disable the generation of VMT loading code
* dbgstabs.pas, dbgdwarf.pas: treat virtual methods of helpers as normal methods
* ncgcal.pas: don't register virtual helper methods for WPO
* ncgrtti.pas: write virtual helper methods as normal methods to RTTI
* nobj.pas: correctly handle final and override cases in helpers
* pdecvar.pas: property getters
* rautils.pas: no VMT offset in records
git-svn-id: branches/svenbarth/classhelpers@17150 -
be used outside the code generator
* renamed tabstractprocdef.requiredargarea into callerargareasize,
and also added calleeargareasize field; added init_paraloc_info(side)
method to init the parameter locations and init those size fields and
replaced all "if not procdef.has_paraloc_info then ..." blocks with
procdef.init_paraloc_info(callersize)"
* moved detection of stack tainting parameters from psub to
symdef/tabstractprocdef
+ added tcallparanode.contains_stack_tainting_call(), which detects
whether a parameter contains a call that makes use of stack paramters
* record for each parameter whether or not any following parameter
contains a call with stack parameters; if not, in case the current
parameter itself is a stack parameter immediately place it in its
final location also for use_fixed_stack platforms rather than
first putting it in a temporary location (part of mantis #17442)
* on use_fixed_stack platforms, always first evaluate parameters
containing a stack tainting call, since those force any preceding
stack parameters of the current call to be stored in a temp location
and copied to the final location afterwards
git-svn-id: trunk@16050 -
-- Zusammenführen der Unterschiede zwischen Projektarchiv-URLs in ».«:
U rtl/arm/setjump.inc
A rtl/arm/thumb2.inc
U rtl/arm/divide.inc
A rtl/embedded/arm/stm32f103.pp
U rtl/inc/system.inc
U compiler/alpha/cgcpu.pas
U compiler/sparc/cgcpu.pas
U compiler/i386/cgcpu.pas
U compiler/ncgld.pas
U compiler/powerpc/cgcpu.pas
U compiler/avr/cgcpu.pas
U compiler/aggas.pas
U compiler/powerpc64/cgcpu.pas
U compiler/x86_64/cgcpu.pas
U compiler/cgobj.pas
U compiler/psystem.pas
U compiler/aasmtai.pas
U compiler/m68k/cgcpu.pas
U compiler/ncgutil.pas
U compiler/rautils.pas
U compiler/arm/raarmgas.pas
U compiler/arm/armatts.inc
U compiler/arm/cgcpu.pas
U compiler/arm/armins.dat
U compiler/arm/rgcpu.pas
U compiler/arm/cpubase.pas
U compiler/arm/agarmgas.pas
U compiler/arm/cpuinfo.pas
U compiler/arm/armop.inc
U compiler/arm/narmadd.pas
U compiler/arm/aoptcpu.pas
U compiler/arm/armatt.inc
U compiler/arm/aasmcpu.pas
U compiler/systems/t_embed.pas
U compiler/psub.pas
U compiler/options.pas
git-svn-id: trunk@13801 -
alignment for each memory reference (mantis #12137, and
test/packages/fcl-registry/tregistry1.pp on sparc). This also
enables better code generation for packed records in many cases.
o several changes were made to the compiler to minimise the chances
of accidentally forgetting to set the alignment of memory references
in the future:
- reference_reset*() now has an extra alignment parameter
- location_reset() can now only be used for non LOC_(C)REFERENCE,
use location_reset_ref() for those (split the tloc enum so the
compiler can catch errors using range checking)
git-svn-id: trunk@12719 -
