Commit Graph

582 Commits

Author SHA1 Message Date
tg74
1ef9cc01e6 avx512 disp8*N
git-svn-id: branches/tg74/avx512@39909 -
2018-10-09 21:19:52 +00:00
tg74
7deacdd036 bugfix avx512 opcodes VFNMSUB231PS,VFPCLASSPS
git-svn-id: branches/tg74/avx512@39783 -
2018-09-21 05:34:04 +00:00
tg74
14d392fd0e avx512 broadcast for special opcodes vcvt...
git-svn-id: branches/tg74/avx512@39779 -
2018-09-19 21:29:49 +00:00
tg74
fba72b280b avx512 broadcast vcvt...,vfpclass...
git-svn-id: branches/tg74/avx512@39778 -
2018-09-19 15:28:15 +00:00
tg74
4265f4d6a5 avx512 broadcast for special opcodes vfpclass.., vcvt...
git-svn-id: branches/tg74/avx512@39768 -
2018-09-19 06:25:42 +00:00
tg74
f3e18cedf6 bugfix opcode definition vrsqrt..., vscale...
git-svn-id: branches/tg74/avx512@39755 -
2018-09-14 09:09:35 +00:00
tg74
865563fc82 bugfixes x86ins.dat avx512-opcodes vpexpand..., vptest..., vrcp...
git-svn-id: branches/tg74/avx512@39754 -
2018-09-14 05:19:28 +00:00
tg74
2c40a09d04 bugfixes x86ins.dat avx512-opcodes vf...
git-svn-id: branches/tg74/avx512@39753 -
2018-09-13 22:01:23 +00:00
tg74
1bc0ecec11 bugfix opcode definition vfmadd132pd/ps
git-svn-id: branches/tg74/avx512@39751 -
2018-09-13 11:04:09 +00:00
tg74
ac26adf7c9 bugfix avx512-opcodes
git-svn-id: branches/tg74/avx512@39745 -
2018-09-12 13:59:29 +00:00
tg74
dd967ecfee remove any gather/scatter opcodes for nights mill
git-svn-id: branches/tg74/avx512@39742 -
2018-09-12 09:59:04 +00:00
tg74
608992ecf5 minor bugfixes avx512 tests
git-svn-id: branches/tg74/avx512@39740 -
2018-09-12 05:03:05 +00:00
tg74
c611e4814a new avx512 opcodes
git-svn-id: branches/tg74/avx512@39720 -
2018-09-10 06:19:45 +00:00
tg74
1d9cbb4dcb new AVX512 opcodes
git-svn-id: branches/tg74/avx512@39705 -
2018-09-03 05:40:44 +00:00
tg74
914e31dbd1 new AVX512 instructions vextracti..,vextractf..
git-svn-id: branches/tg74/avx512@39674 -
2018-08-27 06:06:27 +00:00
tg74
6985da744b change x86ins.dat vmovq for test tasm9
git-svn-id: branches/tg74/avx512@39654 -
2018-08-20 13:31:42 +00:00
tg74
2b1da37d66 new avx512 instructions and bugfixes avx512
git-svn-id: branches/tg74/avx512@39636 -
2018-08-19 10:18:32 +00:00
tg74
867d145e50 support vector operand bcst,{sae},{er} + k-register
git-svn-id: branches/tg74/avx512@39457 -
2018-07-16 17:06:57 +00:00
tg74
4dc5442fa5 support vector operand writemask,zeroflag
git-svn-id: branches/tg74/avx512@39359 -
2018-07-02 20:20:03 +00:00
florian
8c0d5411d0 * dwarf numbers corrected
* zmm14 definition fixed
+ commented definitions for bnd/k registers added
* made reg. cound a longint

git-svn-id: branches/tg74/avx512@39209 -
2018-06-10 14:17:37 +00:00
tg74
31e4d4ef5e AVX512 support for MMRegister xmm16..31 and ymm16..31, zmm0..31, vpaddsb support AVX512
git-svn-id: branches/tg74/avx512@39196 -
2018-06-08 06:53:35 +00:00
Jonas Maebe
4686f61002 * keep track of the temp position separately from the offset in references,
so that they can still be freed after the reference has been changed
    (e.g. in case of array indexing or record field accesses) (mantis #33628)

git-svn-id: trunk@38814 -
2018-04-22 17:03:16 +00:00
nickysn
518cdf9674 * replaced the saved_XXX_registers arrays with virtual methods inside
tcpuparamanager, very similar to the existing get_volatile_registers_XXX. The
  new methods are called get_saved_registers_XXX, where XXX is the register
  type ("int", "address", "fpu" or "mm")

git-svn-id: trunk@38794 -
2018-04-19 21:22:16 +00:00
florian
25c5ee2fc3 * patch by J. Gareth Moreton to fix vectorcall (no effect) for linux,
resolves #33184 and #33542

git-svn-id: trunk@38663 -
2018-04-02 21:14:26 +00:00
florian
8b0bbdcaab * fix flag subregs after r38206
git-svn-id: trunk@38502 -
2018-03-11 20:30:11 +00:00
florian
9b18e39c81 * enable Lea2AddBase and Lea2AddIndex in TX86AsmOptimizer.PostPeepholeOptLea as we have flag tracking now
* some flag allocations fixed

git-svn-id: trunk@38501 -
2018-03-11 20:30:09 +00:00
florian
5fbecc5501 + use TX86AsmOptimizer.OptPass1SHLSAL on x86-64
git-svn-id: trunk@38499 -
2018-03-11 14:35:22 +00:00
marco
f0042a4719 * vcmppd hardcoded primitives like vcmpeqpd.
* required increasing maxinfolen to 9 

git-svn-id: trunk@38404 -
2018-03-03 23:32:54 +00:00
marco
f21a141144 * mantis #32001, add 32 vcmpps variants.
git-svn-id: trunk@38403 -
2018-03-03 23:10:03 +00:00
florian
8c5606b41d + support mmx shifting
git-svn-id: trunk@38367 -
2018-02-27 21:40:12 +00:00
florian
3b779278e2 + (slightly) patch by Emelyanov Roman to add support of SEH directive in FPC internal assembler with INTEL syntax, resolves #29894
git-svn-id: trunk@38331 -
2018-02-24 16:14:08 +00:00
florian
91514da267 * factored out TX86AsmOptimizer.PostPeepholeOptCall
+ use TX86AsmOptimizer.PostPeepholeOptCall on x86-64

git-svn-id: trunk@38278 -
2018-02-17 23:25:01 +00:00
florian
112373a124 * fix passing floats on unix after vectorcall patch
git-svn-id: trunk@38209 -
2018-02-11 17:50:43 +00:00
florian
31f78ea2b6 + implementation of the vectorcall calling convention by J. Gareth Moreton
+ tests

git-svn-id: trunk@38206 -
2018-02-11 17:50:37 +00:00
florian
810acd82b2 * patch by J. Gareth Moreton that makes some improvements to the Peephole Optimizer for x86 and x86-64 code, as well as some cleanup with formatting, code syntax consistency, and debug messages.
- xorq %reg,%reg (identical registers) is now changed to xorl %reg,%reg if doing so removes the REX prefix.
  - movw %bx,%ax; andl $0xffff,%eax, for example, is now changed to movzwl %bx,%eax as long as a conditional operation doesn't follow 'and' (checks to see if the CPU flags are in use).
  - movzbq and movzwq get optimised to movzbl and movzwl respectively if doing so removes the REX prefix.
  - Removal of optimisation code that zero-extends from 32-bit to 64-bit, because there isn't actually a valid combination of opcodes for MOVZX that allows that (for registers,
    just use  MOV). This is not the case with MOVSX.
  - movq is now optimised to movl even if the CPU flags are in use (this stops mov %reg,0 from being optimised to xor %reg,%reg if doing so breaks an algorithm that relies on them).
  - Fixed typo in peephole message regarding movq to movl (it said movd instead).
  - Made the peephole debug messages more consistent in formatting, some of which now have more detail.
* small fixes of the patch

git-svn-id: trunk@38070 -
2018-01-28 14:41:54 +00:00
florian
73fda1ccb6 * factored out OptPass1Sub
+ make use of OptPass1Sub on x86_64 and i8086 as well

git-svn-id: trunk@37572 -
2017-11-10 20:55:22 +00:00
nickysn
ae92973196 + added support for the retw, retnw, retfw, retd, retnd, retfd, retq, retnq and
retfq x86 instructions. These are variants of the ret instruction with the
  return offset size set explicitly, e.g. retfw is a 16-bit far ret (i.e. pops
  a 16-bit offset and a 16-bit segment), retfd is a 32-bit far ret (pops a
  32-bit offset, followed by a 16-bit segment), etc.

git-svn-id: trunk@37571 -
2017-11-10 16:53:29 +00:00
pierre
ba3afefa4c Regenerate register include files after commit 37564: Fix value of NR_DR6 and NR_DR7
git-svn-id: trunk@37565 -
2017-11-07 07:30:42 +00:00
florian
4da4b768ec * factored out PostPeepholeOptTest
+ use PostPeepholeOptTest on x86-64

git-svn-id: trunk@37551 -
2017-11-04 19:10:14 +00:00
florian
3097eaf8ee * made PostPeepholeOptMov a function
git-svn-id: trunk@37550 -
2017-11-04 19:10:12 +00:00
florian
a7ea7fb569 * factored out PostPeepholeOptCmp
+ use PostPeepholeOptCmp for x86_64

git-svn-id: trunk@37549 -
2017-11-04 19:10:09 +00:00
nickysn
80226e3af4 + added an optimization pass, that optimizes x86 references
git-svn-id: trunk@37494 -
2017-10-20 15:55:55 +00:00
nickysn
e8bbc4eef9 + support the xlat x86 instruction syntax with a memory operand. This allows
specifying the address size (e.g. xlat byte ptr [bx] or xlat byte ptr [ebx])

git-svn-id: trunk@37478 -
2017-10-17 16:40:06 +00:00
nickysn
0fb79946a5 + added support for the parameterized versions of the x86 string instructions
(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
  and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
  is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
  with the 186+ 'ins' instruction.

git-svn-id: trunk@37446 -
2017-10-12 00:07:02 +00:00
nickysn
92a52a9f4d + implemented support for instructions with non-native address size on i8086
(16-bit and 32-bit), i386 (16-bit and 32-bit) and x86_64 (32-bit and 64-bit).
  Known bug: 32-bit addresses with an offset have their offset truncated to its
  low 16-bits on i8086

git-svn-id: trunk@37409 -
2017-10-06 15:27:14 +00:00
florian
198c53a908 o patch by J. Gareth "Kit" Moreton, resolves partially issue #32037
* generate instructions with shorter imm on x86-64 if possible

git-svn-id: trunk@37376 -
2017-10-01 18:40:09 +00:00
florian
15b617546e + call TX86AsmOptimizer.OptPass1VOP for logical operations as well
git-svn-id: trunk@37367 -
2017-10-01 14:40:21 +00:00
nickysn
aec03309ef + added CPUX86_HAS_SSE2 to x86 tcpuflags
git-svn-id: trunk@37326 -
2017-09-26 16:02:56 +00:00
nickysn
e701fa8de1 * converted the x86 instruction flags to a set, so they can be extended more
easily and so that all the values are now available to the compiler
  (previously, there were several, which were mapped to the same value and thus
  were only used to make x86ins.dat easier to read)

git-svn-id: trunk@37299 -
2017-09-21 15:48:27 +00:00
nickysn
ab62e2237b * mark the sldt,syscall,sysenter,sysexit,sysret,andn,bextr,rorx,sarx,shlx and
shrx instructions as protected mode only

git-svn-id: trunk@37275 -
2017-09-20 15:43:23 +00:00