m68k/cgcpu.pas, tcg68k:
+ override g_adjust_self_value as we don't do register allocation for the wrapper we need to adjust the Self value using the scratch registers (could be improved however) and we also can not use the offset that the original procedure in tcg uses
* fix g_intf_wrapper by using the correct operations and loading the correct (virtual) method offset
git-svn-id: trunk@25728 -
m68k/cgcpu.pas, tcg68k:
- remove g_save_registers and g_restore_registers which DID NOT CALL inherited!
- also remove commented methods g_save_all_registers & g_restore_all_registers
git-svn-id: trunk@25715 -
- removed the ancient DEBUG_CHARLIE silliness... :)
- moved some repeated code patterns into separate functions
- rewrote most of of tcg68k.a_op_const_reg and tcg68k.a_op_reg_reg
- smarter code generation in tcg68k.a_cmp_const_reg_label
- added support for MULU/MULS on Coldfire in a case which is often used by the CG to index arrays to be used instead of the RTL helpers, this results in a *HUGE* speedup in tw5086 for example
git-svn-id: trunk@25702 -
cgobj.pas, tcg:
* g_save_registers: add the amount of used address registers to size as well
* g_save_registers: save all used address registers
* g_restore_registers: restore all stored address registers
m68k/cpubase.pas:
* rename saved_standard_address_registers to saved_address_registers
all other platform's cpubase.{inc,pas} (except alpha, ia64 and vis which are not up to date):
* add a saved_address_registers variable with one entry of RS_INVALID
At least a "make fullcycle" did complete.
git-svn-id: trunk@25664 -
m68k/cgcpu.pas, tcg68k.g_proc_exit:
* use A0 (which is a volatile register) instead of A3 (which is not) to restore the stack pointer
git-svn-id: trunk@25663 -
this fixes varargs a bit, particularly fixes an unhandled TList bounds exception while compiling packages/fcl-base/src/eventlog.pp
git-svn-id: trunk@25636 -
paramgr.pas, tparamanager:
+ add virtual get_volatile_registers_address method which by default returns an empty set
cgobj.pas, tcg:
* allocallcpuregisters: also allocate address registers if needed
* deallocallcpuregisters: also deallocate address registers if needed
ncgcal.pas, tcgcallnode.pass_generate_code:
* (de)allocate address registers
* keep result from being deallocated if it should be an address register (currently by no architecture...)
m68k/cpupara.pas, tm68kparamanager:
+ get_volatile_registers_address: return a0 and a1 as volatile registers
m68k/n68kmat.pas, tm68kmoddivnode.call_rtl_divmod_reg_reg:
* (de)allocate address registers
git-svn-id: trunk@25633 -
m68k/n68kadd.pas, tn68kadd.second_cmpordinal:
* use the size of the largest operand to select a fiting operand
* ToDo: check whether a sign/zero extend of the value is necessary
git-svn-id: trunk@25628 -
m68k/n68kcnv.pas, tn68kcnv.second_int_to_bool:
* we need to check both the upper and the lower register for a 64-bit value to decide whether it's True or False
git-svn-id: trunk@25625 -
m68k/cgcpu.pas, tcg68k:
* a_load_ref_cgpara: use pashsize instead of paraloc^.size as the latter could be OS_NO and thus a "move" instead of a "move.x" will be generated resulting in a word move when a long or byte move might have been necessary
* a_load_reg_ref: use the smallest size when moving the value to a reference
* a_load_ref_ref: when the size is different always use a temporary register for a ref to ref move
* a_load_ref_ref: when doing a fixed move for Coldfire use the correct ref (that's another embarrasing error...) and size (fixes usage of String[Index] for a const array parameter)
* a_load_ref_reg: use the smallest size when moving the value from a reference
* g_concatcopy: don't use source.alignment as that doesn't contain the correct value and also load the value into the temp register using the correct size (fixes passing of small values as parameters, like chars)
git-svn-id: trunk@25624 -
m68k/cgcpu.pas, tcg68k.g_flags2reg:
* don't sign extend the flag value which was stored to the register, but instead do a "AND 1" on it to reduce it to 1 bit; afterall Booleans in Pascal are either 0 or 1 and not 0 or $FF
+ added test
git-svn-id: trunk@25598 -
Therefor the cpu type (-Cp...) "coldfire" was split up into "isaa", "isaa+", "isab" and "isac". The Linux RTL can currently compiled for "68020", "isab" and "isac". For the other three Bcc.L must be handled differently (only Bcc.B/W supported) and for "68000" also EXT.L needs to be handled differently.
fpcdefs.inc:
+ define CPUCAPABILITIES if capabilities can be set for a certain CPU type (currently ARM, AVR and M68k)
options.pas:
* check for CPUCAPABILITIES instead of specific CPUs
assemble.pas:
- the handling of the CPU type is already done in m68k/ag68kgas.pas, Tm68kGNUAssembler.MakeCmdLine (and thereby already using the gascputypestr array!)
m68k/cpuinfo.pas:
- tcputype: remove "cpu_coldfire"
+ tcputype: add "cpu_isa_a", "cpu_isa_a_p", "cpu_isa_b" and "cpu_isa_c"
+ add "cpu_coldfire" constant which contains all Coldfire specific cpu types
* adjust "cputypestr" and "gascputypestr"
+ add tcpuflags and cpu_capabilities (DBRA restriction was checked with CPUCOLDFIRE, CAS/TAS will be needed for atomic operations and BRAL restriction was discovered during testing of new cpu types)
m68k/cgcpu.pas:
* adjust checks for "cpu_coldfire"
m68k/n68kadd.pas:
* don't use a BRA.L if it is not supported, but (at least for now) a BRA.W
aggas.pas:
* adjusted check for Coldfire
git-svn-id: trunk@25457 -
contains the tcgsize of the entire parameter rather than only of
what is left (-> calculate it from the remaining parameter length)
git-svn-id: trunk@24776 -
m68k/cgcpu.pas, tcg68k:
+ overload "a_loadfpu_ref_cgpara" and use the 64-bit code generator to pass Doubles if they are located in references
Fixes around nearly 100 tests.
git-svn-id: trunk@23597 -
* initialize paraloc^.size to OS_INT instead of leaving it at 0
This fixes tests/test/cg/ttryexc1.pp. The problem was that the raise node generated code which resulted in a word(!) move of the raised object's address to the stack location for fpc_raiseexception. This then resulted in an error when freeing the exception object.
git-svn-id: trunk@23465 -
m68k/aasmcpu.pas, taicpu.spilling_get_operation_type:
* add all Sxx instructions as "operand_write" instructions
m68k/n68kadd.pas, t68kaddnode.getresflags:
* use the correct operation in case of swapped nodes
m68k/cgcpu.pas, tcg68k.g_flags2reg:
- don't move a 0 to the register, because this will CLR it and thus the flags won't be valid anymore...
- NEG would have been the wrong operation (NOT would have been correct), but it isn't needed anyway...
* simplify the method by handling the address register case only when necessary
git-svn-id: trunk@23383 -
use the correct flag for the copy loop: we jump back to the copy code as long as the value is positive aka BPL instead of BMI
This fixes around 30 tests (it fixes a quite bit more, but now some other tests seem to be broken...)
git-svn-id: trunk@23373 -
that the type of the parameters can be determined automatically
o added compilerproc declarations for all helpers called in the compiler
via their assembler name, so we can look up the corresponding procdef
git-svn-id: trunk@23325 -
+ a_op64_reg_reg: add support for "NEG" and "NOT" of 64-bit values
+ a_op64_const_reg: make sure that we know whether a NEG or NOT with a constant is performed
git-svn-id: trunk@22930 -
* in case of copying from the parameter location to the local location we need to use the alignment size for the source as byte/word values are passed as LongInts (this is how the ABI is specified)
git-svn-id: trunk@22924 -
+ add routine "call_rtl_moddiv_reg_reg" which handles the calling of "fpc_div_longint", "fpc_div_dword", "fpc_mod_longint" and "fpc_mod_dword"
* emit_mod_reg_reg & emit_div_reg_reg: use the new method instead of doing the call oneself
=> "Str(SomeInt, SomeStr)" and "Writeln(SomeInt)" now works
git-svn-id: trunk@22893 -
+ add methods "call_rtl_mul_const_reg" and "call_rtl_mul_reg_reg" which can call the RTL helpers "fpc_mul_longint" and "fpc_mul_longword" (based on AVR code)
* use the new call methods for the RTL to correctly pass the parameters (on the stack, not in registers...)
git-svn-id: trunk@22892 -
* don't do a sign_extend, but use the correct move size to copy the const; this fixes the setting of the line ending style inside of "Assign"
=> output of strings does now work correctly!
git-svn-id: trunk@22890 -
TRegNameTable is defined in compiler/rgbase.pas and is an array of
strings, limited to the maximum length of the used register names.
r22792 added a long register name but did not scale the string-size
enough, resulting in the compiler built breaking for arm.
git-svn-id: trunk@22817 -
for "CMP" it is important to note that the first operand (which can be basically a register, a constant or a reference) is substracted from the second operand (which needs to be a data register) and not the other way round
git-svn-id: trunk@22798 -
fixes a couple of arm-embedded stuff,
adds some controllers, start of fpv4_s16 support, for a complete list of
changes see below:
------------------------------------------------------------------------
r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line
Properly do NR_DEFAULTFLAGS detection/allocation/deallocation
------------------------------------------------------------------------
r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line
Fixed flags detections code for wide->short optimization code for Thumb-2
------------------------------------------------------------------------
r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
------------------------------------------------------------------------
r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line
Added register specifications to lpc1768.pp. From Joan Duran
------------------------------------------------------------------------
r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines
Fixed some minor formating issues
Implemented a small heap mananger
Implemented console IO
Changed default LineEnding to CrLf(to ease console IO parsing)
------------------------------------------------------------------------
r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line
Added all STM32F1 configurations
------------------------------------------------------------------------
r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line
Added initial support for the Cortex-M4F FPv4_S16 FPU
------------------------------------------------------------------------
r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line
Added FPv4_d16 FPU instructions, and a few extra registers
------------------------------------------------------------------------
r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for IT block merging
Added a peephole pattern check for UXTB->UXTH chains
------------------------------------------------------------------------
r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines
Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code
Added a number of simple size optimizations for common Thumb-2 instructions
------------------------------------------------------------------------
r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines
Fix optimizations of Thumb-2 code
Fix problem with loading of condition operand for IT instructions
Properly split IT blocks when register allocator tries to spill inside a block.
------------------------------------------------------------------------
r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines
Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts
------------------------------------------------------------------------
r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines
Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader
IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements
------------------------------------------------------------------------
r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines
Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)
git-svn-id: trunk@22792 -
fix the double running of second_pass in the way it was intended to work: check for left.expectloc instead of left.location.loc
git-svn-id: trunk@22788 -
(of which the names had changed from FPC_MUL_LONGWORD->FPC_MUL_DWORD and FPC_MOD_CARDINAL->
FPC_MOD_DWORD).
Also disable the usage of FPU opcodes for Coldfire.
git-svn-id: trunk@22739 -
M68000 CPUs they are nevertheless more restricted in some cases, so these need to be
handled explicitely (especially if symbols are involved).
git-svn-id: trunk@22738 -
* generate special return code for non-68020 CPU which don't support RTD instruction (based on
out code a few lines further down)
git-svn-id: trunk@22736 -
It seems that GNU as needs the syntax "offset(register.size*scale)" if the base address
register is ommited instead of "offset(,register.size*scale)". Now the System unit
assembles and nearly the complete RTL can be built.
git-svn-id: trunk@22734 -
leave "and" and "or" as "and" and "or" as according to the assembly language reference the
assembler should automatically choose the correct instruction (though Coldfire still should
be tested for ORI/ANDI to CCR
git-svn-id: trunk@22733 -
* use andi/ori for constant values
* use a scratch register if target is an address register (there seems to exist an omnious
anda/ora instruction though, but GNU as doesn't seem to handle it... maybe I haven't set
the CPU type correctly, so I'll need to investigate this so we can hopefully remove the
need for a scratch register for certain CPU types ;) )
git-svn-id: trunk@22732 -
* remove comments regarding needed LOC_JUMP implementation
* don't call flags2reg if the location is LOC_JUMP as there isn't a register to set the flags to
(this allows fpc_mul_qword and fpc_mul_int64 to be assembled)
git-svn-id: trunk@22731 -
implement case "LOC_JUMP" (with a more or less blindly copy from
x86/nx86cnv.pas, tx86typeconvnode.second.int_to_bool; this now allows that the system unit can
be compiled, but not yet assembled
git-svn-id: trunk@22728 -
the asmr_d_*_reading messages need an argument which specifies in which style the assembler code
is read; this is most importantly used on i386; on m68k we currently don't have multiple styles,
so simply disable these messages
git-svn-id: trunk@22725 -
