Commit Graph

464 Commits

Author SHA1 Message Date
florian
b2f6214b33 + a_bit_scan_reg_reg gets a flag if src cannot be zero: this simplifies the generated code 2025-02-08 14:27:48 +01:00
florian
f49da05633 * unified g_concatcopy_move 2024-05-15 22:52:24 +02:00
Pierre Muller
922893ddbb Attempt to fix tcalext3 big-endian powerpc64 failure 2023-11-20 01:05:10 +03:00
Nikolay Nikolov
9b8af14f47 + introduced [hl]cg.a_label_pascal_goto_target. It is similar to [hl]cg.a_label
and is called by the code generator, when the label generated is the result of
  a Pascal label.
2023-06-04 05:11:07 +03:00
J. Gareth "Curious Kit" Moreton
5cdef8050b * Fixed bug in register preservation tracking 2023-01-10 22:23:58 +00:00
J. Gareth "Curious Kit" Moreton
67a1d52806 JccAdd2SetccAdd modified to make use of GetIntRegisterBetween 2022-01-08 22:43:41 +00:00
J. Gareth "Curious Kit" Moreton
30166f8eb7 Procedure-saved registers are now recorded for peephole optimizers to use 2022-01-08 22:43:41 +00:00
florian
dca4bde3a2 * unified internal error 2021-09-01 09:31:50 +02:00
florian
c0d75c1c69 * patch Christo Crause: Use LDS for 8 bit references, resolves #38173
git-svn-id: trunk@47700 -
2020-12-06 16:40:30 +00:00
florian
eb098a3d11 * do not reuse a loaded reference for avrtiny in a_op_const*, resolves #38142
git-svn-id: trunk@47612 -
2020-11-27 21:16:31 +00:00
florian
637976e83f * patch by Marģers to unify internal error numbers, resolves #37888
git-svn-id: trunk@47103 -
2020-10-13 19:59:01 +00:00
florian
d7fe9914a7 + introduce tcgobj.a_loadfpu_reg_intreg
+ make use of it in tcgtypeconvnode.second_nothing
  + Xtensa: implementation of a_tcgcpu.a_loadfpu_intreg_reg and tcgcpu.a_loadfpu_reg_intreg

git-svn-id: trunk@46858 -
2020-09-12 21:23:57 +00:00
pierre
fdb1cd38ab Disable limitation of handling of negative shift values, can be enalbed again by setting LIMIT_NEG_SHIFTVALUES macro
git-svn-id: trunk@46221 -
2020-08-04 07:45:03 +00:00
pierre
02fd6f6e54 * tcg.a_load_cgparaloc_ref: Always enable SHR instruction for mips/mipsel CPUs
This is normally only used on big-endian targets, to re-convert records
    of size < OS_INT into values fitting inside the byte size of the record,
    after it was left-shifted to comply with ABI stipulating it but be
    writable as a full-size register into a OS_INT size memory.

git-svn-id: trunk@45783 -
2020-07-14 06:00:23 +00:00
Jonas Maebe
e7d1a77f9a * rename the ARM/AArch64-Darwin targets to ARM/AArch64-iOS
* rename the m68k/PowerPC-MacOS targets to m68k/PowerPC-MacOSClassic
  * repurpose the AArch64/Darwin target for AArch64/macOS
   o make AArch64-Darwin default target for a hosted AArch64-Darwin compiler

git-svn-id: trunk@45758 -
2020-07-10 21:52:24 +00:00
nickysn
0f6ab0de17 * handle LOC_(C)SUBSETREG/REF in second_NegNot_assign
* changed the way OP_NEG and OP_NOT are handled in op_reg_ref, in order to be
  consistent with op_reg_reg
* introduced op_reg,op_ref,op_subsetreg,op_subsetref and op_loc for the unary
  operations only (OP_NEG,OP_NOT)

git-svn-id: trunk@45302 -
2020-05-07 02:43:02 +00:00
Jonas Maebe
3f6ad30b69 * don't convert the fpu parameters size from tcgsize -> int -> float_tcgsize
if not required, to avoid translating OS_C64 into OS_F64 (fix for x86
    test failures after r45205)

git-svn-id: trunk@45221 -
2020-05-02 13:17:21 +00:00
Jonas Maebe
722ad1ff7b * support floating point parameters split over multiple locations, including
integer registers, for homogeneous records/arrays on ppc64le (related to
    mantis #36934)

git-svn-id: trunk@45205 -
2020-05-01 13:02:48 +00:00
florian
9e0337f248 * do not use an extra register in tcginlinenode.second_IncDec if not needed
git-svn-id: trunk@45177 -
2020-04-29 20:01:53 +00:00
nickysn
70e90175e5 * fix warnings in cgobj for 8-bit alu cpus
git-svn-id: branches/z80@44825 -
2020-04-19 04:30:08 +00:00
nickysn
bf8d560cc6 * treat all Z80 registers as 8-bit
git-svn-id: branches/z80@44532 -
2020-04-03 18:53:10 +00:00
nickysn
4b281dd6c9 * changed the ifndef avr to ifdef avr in GetNextReg
git-svn-id: branches/z80@44522 -
2020-04-02 23:05:49 +00:00
nickysn
71cadc0a3e * moved the AVR-specific comment next to the AVR specific code
git-svn-id: branches/z80@44521 -
2020-04-02 23:04:45 +00:00
nickysn
54811831b5 - disable the check for R_SUBWHOLE in GetNextReg for Z80
git-svn-id: branches/z80@44520 -
2020-04-02 23:02:55 +00:00
pierre
41e554067a Fix handling of parameters with size below the size of a full register
git-svn-id: trunk@44380 -
2020-03-28 13:13:04 +00:00
florian
b7c6e01b03 * cleaning up tcgsize: it makes no sense to declare every combination and type
the different vector types must be either handled in the high level cg or
    by using the shuffle parameter

git-svn-id: trunk@43860 -
2020-01-04 21:54:53 +00:00
svenbarth
6f584333e5 * symbols called by g_call might need to be imported from dynamic packages as well
git-svn-id: trunk@43538 -
2019-11-21 21:44:29 +00:00
florian
d275e7a7e6 * removed accidently committed debug statement
git-svn-id: trunk@43413 -
2019-11-07 21:12:47 +00:00
florian
c8f746b881 * do not allocate an extra register for some integer operations if not needed
git-svn-id: trunk@43412 -
2019-11-07 21:08:08 +00:00
florian
b3ed34592f + software handling of exceptions on arm
* reworked software handling of exceptions so they can be check lazily

git-svn-id: trunk@42525 -
2019-07-28 21:06:36 +00:00
Jonas Maebe
281b3ad276 * fix case completeness and unreachable code warnings in compiler that would
be introduced by the next commit

git-svn-id: trunk@42046 -
2019-05-12 14:29:03 +00:00
Jonas Maebe
d99d1f1f30 * let the ARM code generator use the generic tcg.a_load_ref_cgpara() instead
of its own buggy version
   o added support to the generic version to override part of the functionality
     needed to implement an ARM quirk

git-svn-id: trunk@41335 -
2019-02-16 10:45:46 +00:00
florian
9f16c34329 + initial work for tls-based threadvar support on arm-linux
git-svn-id: trunk@40267 -
2018-11-07 22:02:58 +00:00
yury
2b459b30d2 * Optimized generic implementations of tcg.a_op_const_ref() and tcg.a_op_reg_ref() for PIC and CPUs which need 2 or more instructions to load a symbol's value by reference.
First the symbol's address is taken and then it is used to load the value and also store the result. It eliminates extra calculation of the symbol's address needed to store the result.
  x86 and other CPUs which can handle refs ops directly or more efficiently already have overloaded versions of these methods and are not affected by this change.

git-svn-id: trunk@40050 -
2018-10-27 11:32:22 +00:00
florian
3c69f9a066 + basic infrastructure to generate code for floating point exception
checking for CPUs without floating point exception support

git-svn-id: branches/laksen/riscv_new@39637 -
2018-08-19 10:54:45 +00:00
Jonas Maebe
d69ad8fa41 * removed temppos field again from parameter locations: they're not allocated
by the temp manager of the current procedure

git-svn-id: trunk@38858 -
2018-04-27 19:18:55 +00:00
Jonas Maebe
4686f61002 * keep track of the temp position separately from the offset in references,
so that they can still be freed after the reference has been changed
    (e.g. in case of array indexing or record field accesses) (mantis #33628)

git-svn-id: trunk@38814 -
2018-04-22 17:03:16 +00:00
nickysn
518cdf9674 * replaced the saved_XXX_registers arrays with virtual methods inside
tcpuparamanager, very similar to the existing get_volatile_registers_XXX. The
  new methods are called get_saved_registers_XXX, where XXX is the register
  type ("int", "address", "fpu" or "mm")

git-svn-id: trunk@38794 -
2018-04-19 21:22:16 +00:00
florian
f08d3fdf8f * moved execution weight calculation into a separate pass, so the info is available already available before the code generation pass if needed
git-svn-id: trunk@38717 -
2018-04-08 20:51:27 +00:00
florian
d86ffb9bfb + tcg.a_op_loc_reg
+ optimized tx86addnode.second_ordinal for x86

git-svn-id: trunk@38500 -
2018-03-11 16:32:26 +00:00
pierre
c63981e5b5 Fix msdos failure due to copy/paste error in previous commit
git-svn-id: trunk@37611 -
2017-11-20 21:45:29 +00:00
florian
010a6f5016 + shift by 8 and 16 on 8 and 16 bit cpus by simple register moves
git-svn-id: trunk@37606 -
2017-11-19 18:05:18 +00:00
florian
f0c237a159 + let a_load_loc_reg handle also LOC_*MMREGISTER as we have loadmm_*intreg*
git-svn-id: trunk@37372 -
2017-10-01 16:13:18 +00:00
florian
9ef646e3c5 * fix avr for new GetNextReg behaviour
* some wrong GetNextReg usage in the avr code generator fixed

git-svn-id: trunk@37316 -
2017-09-24 20:51:05 +00:00
nickysn
c8b351fb67 + added check in GetNextReg(), so it halts with an internal error, if called on
a register, that isn't supposed to have a "next" register allocated

git-svn-id: trunk@37185 -
2017-09-11 18:23:14 +00:00
nickysn
db09759763 * also integrated the getnextreg() implementation for 8-bit and 16-bit alus from
the avr and i8086 code generators into the base tcg class

git-svn-id: trunk@37182 -
2017-09-11 15:47:39 +00:00
nickysn
cf28b202eb * integrated the getintregister() implementation for 8-bit and 16-bit alus from
the avr and i8086 code generators into the base tcg class (so it can be reused
  by other 8-bit and 16-bit targets)

git-svn-id: trunk@37181 -
2017-09-11 15:23:59 +00:00
nickysn
ddba821561 * GetNextReg(), used by 16-bit and 8-bit code generators (i8086 and avr) moved
from cpubase unit to a method in the tcg class. The reason for doing that is
  that this is now a standard part of the 16-bit and 8-bit code generators and
  moving to the tcg class allows doing extra checks (not done yet, but for
  example, in the future, we can keep track of whether there was an extra
  register allocated with getintregister and halt with an internalerror in case
  GetNextReg() is called for registers, which weren't allocated as a part of a
  sequence, therefore catching a certain class of 8-bit and 16-bit code
  generator bugs at compile time, instead of generating wrong code).
- removed GetLastReg() from avr's cpubase unit, because it isn't used for
  anything. It might be added to the tcg class, in case it's ever needed, but
  for now I've left it out.
* GetOffsetReg() and GetOffsetReg64() were also moved to the tcg unit.

git-svn-id: trunk@37180 -
2017-09-11 14:53:06 +00:00
florian
4d5a94644f * do not call a_load_reg_reg with tosize=OS_NO
git-svn-id: trunk@37055 -
2017-08-24 20:09:15 +00:00
florian
99ce914a61 * fix tcg.a_load_cgparaloc_ref for ref. sizes of 7 on little endian systems
git-svn-id: trunk@37002 -
2017-08-21 09:08:02 +00:00