Commit Graph

485 Commits

Author SHA1 Message Date
pierre
019a8b66dc Transform internal error into error message for seg(procvar) with is not usable for some i8086 memory models
git-svn-id: trunk@38219 -
2018-02-12 10:07:35 +00:00
florian
6400d612e8 + seg(<procvardef>) returns the segment stored in the procedure variable
git-svn-id: trunk@38216 -
2018-02-11 22:26:01 +00:00
florian
31f78ea2b6 + implementation of the vectorcall calling convention by J. Gareth Moreton
+ tests

git-svn-id: trunk@38206 -
2018-02-11 17:50:37 +00:00
florian
980c689d37 + Peephole optimizer MovPush2Push
git-svn-id: trunk@38195 -
2018-02-10 22:20:04 +00:00
florian
09af451c2e * try to get rid at least of one mov when looking for les/lds optimization
+ debug messages

git-svn-id: trunk@38191 -
2018-02-10 22:19:57 +00:00
nickysn
2019e622e1 * fixed typed constants, initialized with Ofs(proc) in modes TP and DELPHI as well
git-svn-id: trunk@38134 -
2018-02-06 13:24:15 +00:00
nickysn
e23a13a482 * fixed seg(proc) in tp and delphi modes in all i8086 memory models
git-svn-id: trunk@38133 -
2018-02-06 13:00:08 +00:00
nickysn
899707979a - removed debug writeln, committed by accident in r37727
git-svn-id: trunk@38123 -
2018-02-05 16:39:31 +00:00
nickysn
fe7fb70e2c * fixed the handling of Ofs(x) typed constants on i8086; previously, they would
sometimes produce a far pointer constant (depending on the memory model and
  the type of 'x'), which would accidentally work for single constants, but will
  fail for consts, which are a part of a record or an array. This fixes e.g.
  const c:array[0..1] of word=(Ofs(a),Ofs(b)); in all memory models

git-svn-id: trunk@38121 -
2018-02-05 16:12:20 +00:00
nickysn
614755d799 * fixed the handling of Seg(proc) typed constants on i8086
git-svn-id: trunk@38120 -
2018-02-05 16:07:57 +00:00
nickysn
0119e7afb3 * changed the codepointer type in the i8086 small and compact memory models from
nearpointer to nearcspointer

git-svn-id: trunk@37730 -
2017-12-14 17:36:15 +00:00
nickysn
ae52295232 * fixes for Seg(proc) for i8086
git-svn-id: trunk@37727 -
2017-12-13 16:56:01 +00:00
nickysn
8d18dafe34 * in the i8086 load node, when generating static/global var access to variables
in the default data segment, set their treference.segment to NR_DS, in order
  to avoid creating redundant segment relocations to the default data segment
  (which is a problem with win16 multiple instance applications). Redundant
  segment overrides are stripped later anyway, so it doesn't hurt the generated
  code.

git-svn-id: trunk@37715 -
2017-12-11 20:06:42 +00:00
nickysn
04f0029b77 - don't generate addr_seg relocations for the Seg() directive on i8086, if the
load node didn't fill the segment value in the treference record; instead,
  just use the default segment for the reference

git-svn-id: trunk@37713 -
2017-12-11 17:18:07 +00:00
nickysn
b571f48735 * fixed the return type of FarAddr(), so that it is assignment compatible to
typed far pointers as well

git-svn-id: trunk@37629 -
2017-11-27 19:42:36 +00:00
nickysn
78e0f6c68b + added an i8086-specific FarAddr() function, similar to Addr(), but always
returns a far pointer, regardless of the current memory model

git-svn-id: trunk@37628 -
2017-11-27 16:41:48 +00:00
nickysn
4fc2fa7899 * alloc/dealloc NR_DEFAULTFLAGS in the a_cmp_* methods in the i8086 code
generator

git-svn-id: trunk@37601 -
2017-11-17 19:28:37 +00:00
florian
73fda1ccb6 * factored out OptPass1Sub
+ make use of OptPass1Sub on x86_64 and i8086 as well

git-svn-id: trunk@37572 -
2017-11-10 20:55:22 +00:00
nickysn
ae92973196 + added support for the retw, retnw, retfw, retd, retnd, retfd, retq, retnq and
retfq x86 instructions. These are variants of the ret instruction with the
  return offset size set explicitly, e.g. retfw is a 16-bit far ret (i.e. pops
  a 16-bit offset and a 16-bit segment), retfd is a 32-bit far ret (pops a
  32-bit offset, followed by a 16-bit segment), etc.

git-svn-id: trunk@37571 -
2017-11-10 16:53:29 +00:00
pierre
ba3afefa4c Regenerate register include files after commit 37564: Fix value of NR_DR6 and NR_DR7
git-svn-id: trunk@37565 -
2017-11-07 07:30:42 +00:00
nickysn
034b753e10 * commented out PostPeepholeOptMov, because it breaks the pascal port of cwsdpmi
git-svn-id: trunk@37563 -
2017-11-06 23:30:11 +00:00
florian
c36c4d838d + PostPeepHoleOptsCpu for i8086
git-svn-id: trunk@37552 -
2017-11-04 19:10:15 +00:00
nickysn
303309b28f + added support for 'external far' variables for i8086
git-svn-id: trunk@37532 -
2017-10-30 18:03:44 +00:00
nickysn
d220d6f2c6 * use get_default_segment_of_ref() in the seg() handling on i8086
git-svn-id: trunk@37510 -
2017-10-23 14:55:52 +00:00
nickysn
80226e3af4 + added an optimization pass, that optimizes x86 references
git-svn-id: trunk@37494 -
2017-10-20 15:55:55 +00:00
nickysn
e8bbc4eef9 + support the xlat x86 instruction syntax with a memory operand. This allows
specifying the address size (e.g. xlat byte ptr [bx] or xlat byte ptr [ebx])

git-svn-id: trunk@37478 -
2017-10-17 16:40:06 +00:00
nickysn
0fb79946a5 + added support for the parameterized versions of the x86 string instructions
(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
  and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
  is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
  with the 186+ 'ins' instruction.

git-svn-id: trunk@37446 -
2017-10-12 00:07:02 +00:00
nickysn
92a52a9f4d + implemented support for instructions with non-native address size on i8086
(16-bit and 32-bit), i386 (16-bit and 32-bit) and x86_64 (32-bit and 64-bit).
  Known bug: 32-bit addresses with an offset have their offset truncated to its
  low 16-bits on i8086

git-svn-id: trunk@37409 -
2017-10-06 15:27:14 +00:00
nickysn
aec03309ef + added CPUX86_HAS_SSE2 to x86 tcpuflags
git-svn-id: trunk@37326 -
2017-09-26 16:02:56 +00:00
nickysn
e701fa8de1 * converted the x86 instruction flags to a set, so they can be extended more
easily and so that all the values are now available to the compiler
  (previously, there were several, which were mapped to the same value and thus
  were only used to make x86ins.dat easier to read)

git-svn-id: trunk@37299 -
2017-09-21 15:48:27 +00:00
nickysn
ab62e2237b * mark the sldt,syscall,sysenter,sysexit,sysret,andn,bextr,rorx,sarx,shlx and
shrx instructions as protected mode only

git-svn-id: trunk@37275 -
2017-09-20 15:43:23 +00:00
nickysn
db09759763 * also integrated the getnextreg() implementation for 8-bit and 16-bit alus from
the avr and i8086 code generators into the base tcg class

git-svn-id: trunk@37182 -
2017-09-11 15:47:39 +00:00
nickysn
cf28b202eb * integrated the getintregister() implementation for 8-bit and 16-bit alus from
the avr and i8086 code generators into the base tcg class (so it can be reused
  by other 8-bit and 16-bit targets)

git-svn-id: trunk@37181 -
2017-09-11 15:23:59 +00:00
nickysn
ddba821561 * GetNextReg(), used by 16-bit and 8-bit code generators (i8086 and avr) moved
from cpubase unit to a method in the tcg class. The reason for doing that is
  that this is now a standard part of the 16-bit and 8-bit code generators and
  moving to the tcg class allows doing extra checks (not done yet, but for
  example, in the future, we can keep track of whether there was an extra
  register allocated with getintregister and halt with an internalerror in case
  GetNextReg() is called for registers, which weren't allocated as a part of a
  sequence, therefore catching a certain class of 8-bit and 16-bit code
  generator bugs at compile time, instead of generating wrong code).
- removed GetLastReg() from avr's cpubase unit, because it isn't used for
  anything. It might be added to the tcg class, in case it's ever needed, but
  for now I've left it out.
* GetOffsetReg() and GetOffsetReg64() were also moved to the tcg unit.

git-svn-id: trunk@37180 -
2017-09-11 14:53:06 +00:00
nickysn
4e489f2b33 + generate faster, branchless code for abs(int64) on i8086
git-svn-id: trunk@37172 -
2017-09-10 18:58:45 +00:00
nickysn
ebf4f715e8 + added a i8086 specific implementation of 32-bit abs(), which generates even
better code

git-svn-id: trunk@37162 -
2017-09-10 12:28:00 +00:00
nickysn
74dad2099e + added tcpuflags and cpu_capabilities to i8086's cpuinfo.pas
git-svn-id: trunk@37155 -
2017-09-08 14:38:40 +00:00
nickysn
aa415bfc6b + optimized division by negative power of 2 constants in the i8086 code
generator as well

git-svn-id: trunk@37004 -
2017-08-21 11:56:11 +00:00
nickysn
b92b0eac83 * also improve the code, generated for signed division by 2 on i8086, when
optimize cpu target is 486+, by replacing the sequence
    sar reg, 15
    and reg, 1
  with:
    shr reg, 15

git-svn-id: trunk@36807 -
2017-07-28 15:38:40 +00:00
nickysn
bb7cd4866d * corrected comment in x86 division code - it said "signed", when it actually meant "negative"
git-svn-id: trunk@36799 -
2017-07-27 15:04:56 +00:00
pierre
8b6563bef2 Generate error if stack size of a procedure/function is bigger than globally allocated stack size
git-svn-id: trunk@36506 -
2017-06-16 07:47:17 +00:00
florian
912e6d129a * fix modification flags for *ROUND*
git-svn-id: trunk@36280 -
2017-05-21 11:12:57 +00:00
nickysn
efc5e339d0 * use an enum instead of integer constants to represent inline numbers
* compinnr.inc include file converted to a unit
* inline number field size stored in ppu increased from byte to longint
* inlines in the parse tree (when written with the -vp option) now printed with
  their enum name, instead of number

git-svn-id: trunk@36174 -
2017-05-10 14:41:43 +00:00
florian
4a43d992f5 * unified usage of MatchOpType
* fixed generic MatchOpType

git-svn-id: trunk@36145 -
2017-05-07 16:18:33 +00:00
nickysn
af48d176ec + precise flag information for the ucomiss,ucomisd,vucomiss and vucomisd x86 instructions
git-svn-id: trunk@36115 -
2017-05-05 13:41:43 +00:00
nickysn
4e4e5d6d07 + allocate and free the flags register (when necessary), when generating code
for OP_SHR,OP_SHL and OP_SAR in tcg64f8086.a_op64_const_reg

git-svn-id: trunk@36021 -
2017-04-30 01:25:54 +00:00
nickysn
b8c4dd9e18 + implemented 64-bit OP_SHR,OP_SHL and OP_SAR in a_op64_reg_reg for i8086 and
use it in the shl/shr node for code generation.

git-svn-id: trunk@36018 -
2017-04-29 21:57:48 +00:00
nickysn
a82c89d894 + implemented OP_SHR,OP_SHL and OP_SAR in a_op64_const_reg for i8086. The shlshr
node now uses them for 64-bit shift by constant.

git-svn-id: trunk@36017 -
2017-04-29 20:58:55 +00:00
nickysn
aee000a773 * i8086's TCpuAsmOptimizer made a descendant of TX86AsmOptimizer
git-svn-id: trunk@35985 -
2017-04-27 18:22:14 +00:00
nickysn
ff1ee6836d + fix RegReadByInstruction for the x86 MOVSD instruction
git-svn-id: trunk@35968 -
2017-04-27 14:42:08 +00:00
nickysn
c8487c4150 + added individual bits of the x86 flags register as subregisters
git-svn-id: trunk@35955 -
2017-04-26 13:52:52 +00:00
nickysn
5f66f5cebb + distinguish between x86 flags subregisters: flags, eflags and rflags
git-svn-id: trunk@35953 -
2017-04-25 16:10:43 +00:00
nickysn
65977f9f27 + implemented OP_ROL and OP_ROR in tcg8086.a_op_reg_reg and .a_op_reg_ref
git-svn-id: trunk@35952 -
2017-04-25 13:46:20 +00:00
nickysn
8c200fcfba + implemented OP_SHR,OP_SHL,OP_SAR,OP_ROL and OP_ROR in tcg8086.a_op_const_ref
git-svn-id: trunk@35945 -
2017-04-25 11:06:12 +00:00
nickysn
50b1c9c088 + implemented 32-bit OP_SHR,OP_SHL and OP_SAR in tcg8086.a_op_reg_ref
git-svn-id: trunk@35935 -
2017-04-24 13:43:18 +00:00
nickysn
0c244046a9 * proper register change info for the movs,cmps and scas x86 string instructions
(movsd still todo, because of the overlap with the sse2 instruction)

git-svn-id: trunk@35929 -
2017-04-23 21:30:25 +00:00
nickysn
1d34e96064 + added x86 instruction flag Ch_RFLAGScc, indicating instructions that read
specific bits from the flags register, according to their condition (used by
  Jcc/SETcc/CMOVcc)

git-svn-id: trunk@35907 -
2017-04-22 22:07:05 +00:00
nickysn
1146b7c12c + added detailed information for individual flag bits use for most x86
instructions. Not used by the compiler yet, but may allow more
  optimizations in the future.

git-svn-id: trunk@35882 -
2017-04-21 23:03:33 +00:00
nickysn
869f395a31 + added knowledge to the compiler for the x86 instructions, that don't read
their input registers, in case both parameters are the same register (e.g.
  xor eax, eax; sub eax, eax; etc.)

git-svn-id: trunk@35861 -
2017-04-20 15:11:56 +00:00
nickysn
328d546155 + extend the i8086 peephole optimization that converts certain sequences to lds
and les instructions to also support the lss, lfs and lgs instructions on i386
  (won't be generated by the current code generator, but might become useful in
  the future, if we start using the fs and gs segment registers as well)

git-svn-id: trunk@35858 -
2017-04-20 13:00:26 +00:00
nickysn
12a1ad66b2 + added the Ch_RDirFlag change attribute to the STOSx instructions (previously
was missing, due to the 3 attributes per instruction limit)

git-svn-id: trunk@35855 -
2017-04-19 20:23:24 +00:00
nickysn
9303a8f61a * changed the x86 TInsProp.Ch structure from a 3-element array to a pascal set;
this removes the limit of 3 Ch_XXX flags per instruction (thus allowing adding
  more precise flags, e.g. for tracking only certain bits of the flags register,
  etc.) and avoids the ugliness of having the Ch_None filler, which makes
  x86ins.dat less readable.

git-svn-id: trunk@35850 -
2017-04-19 16:48:35 +00:00
nickysn
189e49998c * fixes to the x86 instruction flags tracking attributes:
* AAA and AAS also read flags (AF)
  * CMC reads and writes flags (it inverts CF)
  * CMPSx and SCASx write flags
  * CMPSx, SCASx, LODSx, STOSx, MOVSx read the direction flag
  * NOT doesn't affect flags
  * REP isn't affected by and doesn't affect flags
  * REPE/REPNE/REPZ/REPNZ/REPC/REPNC don't write flags, only read them
  * ROL and ROR don't read flags
  * SAL doesn't read flags
  * SHLD and SHRD don't read flags

git-svn-id: trunk@35849 -
2017-04-19 15:42:50 +00:00
nickysn
7ee0c07b8d + added flags register tracking for many i8086 operations
git-svn-id: trunk@35848 -
2017-04-19 13:46:20 +00:00
nickysn
256dc546ac + implemented the in_neg_assign_x and in_not_assign_x inline nodes, which will
be used (TBD in a future commit) for optimizing x:=-x and x:=not x on CPUs
  that support performing these operations directly in memory (such as x86)

git-svn-id: trunk@35749 -
2017-04-07 16:02:40 +00:00
nickysn
9093047a7a * fixed a bug in the i8086 32-bit rol/ror code generation method rm_fast_386
git-svn-id: trunk@35745 -
2017-04-06 15:55:43 +00:00
nickysn
1560f20e7f + implemented other 32-bit rol/ror by const methods for i8086 and added a
(hopefully) reasonable selection for them for all consts between 1 and 31

git-svn-id: trunk@35744 -
2017-04-06 15:41:39 +00:00
nickysn
0fd860d9e7 * refactored the code generation for 32-bit rol/ror by const for i8086, so it
uses less code repetition and allow choosing various methods (some of which
  will be implemented later and selected, according to the cpu and optimization
  settings (size vs speed))

git-svn-id: trunk@35743 -
2017-04-06 13:59:53 +00:00
nickysn
d5e33cce7f * generate better i8086 code for ror32 by 1 and 17
git-svn-id: trunk@35741 -
2017-04-05 14:16:00 +00:00
nickysn
321876252b + enabled the rol/ror intrinsic on i8086
git-svn-id: trunk@35734 -
2017-04-04 22:37:58 +00:00
nickysn
b957b65ec8 * generate better i8086 code for 64-bit shl/shr, by masking the shift count by 63
git-svn-id: trunk@35730 -
2017-04-04 17:58:00 +00:00
nickysn
76cb419241 * use 16-bit 386+ instructions (shld,shrd) for performing fast 32-bit
shl/shr/sar on i8086, in a_op_const_reg, when the target CPU is set to 80386
  or later

git-svn-id: trunk@35726 -
2017-04-04 14:40:29 +00:00
nickysn
0ab4f01668 * implemented fast (loopless) 32-bit shift by constant for 8086 as well
git-svn-id: trunk@35725 -
2017-04-03 21:04:59 +00:00
nickysn
0f2ad7b712 * generate faster (i.e. loopless) code for 32-bit shl/shr/sar by const on 186+
git-svn-id: trunk@35723 -
2017-04-03 20:37:21 +00:00
nickysn
f0a63fa895 + added an optimized implementation of a_op64_reg_ref for i8086; this improves
the generated code on i8086 for things like inc(int64_var,int64_var) and
  dec(int64_var,int64_var)

git-svn-id: trunk@35657 -
2017-03-25 18:45:31 +00:00
Jonas Maebe
880d438704 * renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can
inherit from it for LLVM without a thousand ifdefs

git-svn-id: trunk@35141 -
2016-12-16 22:41:21 +00:00
Jonas Maebe
a25ebbba3e + added volatility information to all memory references
o separate information for reading and writing, because e.g. in a
     try-block, only the writes to local variables and parameters are
     volatile (they have to be committed immediately in case the next
     instruction causes an exception)
   o for now, only references to absolute memory addresses are marked
     as volatile
   o the volatily information is (should be) properly maintained throughout
     all code generators for all archictures with this patch
   o no optimizers or other compiler infrastructure uses the volatility
     information yet
   o this functionality is not (yet) exposed at the language level, it
     is only for internal code generator use right now

git-svn-id: trunk@34996 -
2016-11-27 18:17:37 +00:00
sergei
133fcb5ab2 * Fixed VMOVQ instruction encoding, now assembles correctly also in 32-bit code.
+ Test

git-svn-id: trunk@34949 -
2016-11-21 13:59:44 +00:00
sergei
ebe134febc * Fixed memory reference size for MOVSS instruction, Mantis #29954.
git-svn-id: trunk@34943 -
2016-11-21 03:31:25 +00:00
sergei
870fda34d5 * x86 AT&T reader and writer: cleaned up usage of attsufMM suffix:
* It is now only used to select size of vector instructions (i.e. 128 or 256 bits)
  * Scalar instructions reverted to use attsufINT suffix (selecting between 32 or 64 bits).
  * Additionally, vcvtsi2sd and vcvtsi2ss with rm64 operand are x86_64 only.

git-svn-id: trunk@34942 -
2016-11-21 02:07:13 +00:00
sergei
edf943a4f6 * Changed memory operand size for VMOVSS instruction to 32 bits, Mantis #29957.
git-svn-id: trunk@34918 -
2016-11-18 23:37:01 +00:00
florian
56252d59f0 + support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
git-svn-id: trunk@34917 -
2016-11-18 20:19:39 +00:00
pierre
abaea9959f Fix parameter loading of FPC_CHECKPOINTER to handle correctly references with offsets
git-svn-id: trunk@34743 -
2016-10-18 21:48:59 +00:00
nickysn
35b0201002 + added an unsigned counterpart to tpointerdef.pointer_arithmetic_it_type (needed by inc/dec)
git-svn-id: trunk@34653 -
2016-10-08 11:45:24 +00:00
nickysn
f76722b6c3 * fixed i8086's tcpupointerdef.pointer_arithmetic_int_type and
.pointer_subtraction_result_type methods after r34607

git-svn-id: trunk@34613 -
2016-10-04 00:06:50 +00:00
nickysn
481a8ec58d * for pointers, converted to arrays, use a newly added virtual method
tpointerdef.converted_pointer_to_array_range_type to obtain their integer
  range type, instead of using ptrsinttype

git-svn-id: trunk@34612 -
2016-10-04 00:01:06 +00:00
svenbarth
c8202061dc * get rid of addr_load_indirect again by having tcgx86 provide an internal implementation of both make_simple_ref() and a_load_ref_reg() so that make_direct_ref() can call the latter (and the latter the former) without fear of inifinite recursive calls due to the symbol; a_load_ref_reg() is additionally declared as "final" as a_load_ref_reg_internal() needs to be overloaded instead (which is the case for tcg8086)
git-svn-id: trunk@34579 -
2016-09-30 14:01:02 +00:00
pierre
4d09dfca95 Remember usage of checkpointer (-gc) option:
Use new cs_checkpointer_called moduleswitches set element.
     Use new uf_checkpointer_called PPU flag (reusing obsolete uf_local_browser flag value)
     Emit warning if compiled library/program has any code using checkpointer.
  
 * ppu.pas: New constant: uf_checkpointer_called
 * globtype.pas: New constant: cs_checkpointer_called
 * fppu.pas: Set uf_checkpointer_called flag if cs_checkpointer_called is set in current_settings.module_switches
 * i8086/n8086mem.pas: Include cs_checkpointer_called in current_settings.moduleswitches
 *  ncgmem.pas: Likewise.
 * msg/errore.msg: Add new message saying that -gc and -Ur options are incompatible
   Add description to -gc option, saying it is experimental.
   Add warning at link time for program/library if checkpointer is used in any unit or main code.
 * options.pas: if -gc and -Ur options are used, never enable checkpointer code,
   instead output a warning that release is incompatible with -gc option.
 * pmodules.pas: proc_program: Check all modules for uf_checkpointer_called flag,
   emit a warning if checkpointer is used.
 * utils/ppuutils/ppudump.pp: Add code for uf_codepointer_called option.

git-svn-id: trunk@34567 -
2016-09-27 14:46:09 +00:00
Jonas Maebe
0afbe85aab * various memory reference alignment fixes
git-svn-id: trunk@34544 -
2016-09-20 21:43:19 +00:00
Jonas Maebe
aa1be3276f - removed default value of _typ parameter of TAsmData.(Weak)RefAsmSymbol():
it was AT_NONE, which is invalid and should never be used
  * explicitly pass the correct value for all calls to those methods elsewhere
    in the compiler

git-svn-id: trunk@34250 -
2016-08-05 07:09:16 +00:00
Jonas Maebe
a0efde8167 * automatically generate necessary indirect symbols when a new assembler
symbol is defined
   o removed all places where AB_INDIRECT symbols were explicitly generated
   o only generate AB_INDIRECT symbols for AT_DATA on systems_indirect_var_imports
   o for some symbols an indirect symbol is always required (because they are
     dereferenced by code in RTL units) -> use new AT_DATA_FORCEINDIRECT type

git-svn-id: trunk@34165 -
2016-07-20 20:53:03 +00:00
Jonas Maebe
1cb8c0d00c * specify the def of assembler level symbols defined via
tasmdata.DefineAsmSymbol() and all routines that call it
   o will be used to automatically generate AB_INDIRECT sybols when
     necessary

git-svn-id: trunk@34164 -
2016-07-20 20:52:59 +00:00
nickysn
ac5658470e + use the 16-bit movsx and movzx instructions on 386+ in tcg8086.a_load_ref_reg
as well

git-svn-id: trunk@34050 -
2016-07-02 17:05:48 +00:00
nickysn
a5f1ae97d4 + make use of the 16-bit movsx and movzx instructions in tcg8086.a_load_reg_reg
when the cpu target is 80386 or later

git-svn-id: trunk@34046 -
2016-07-02 14:06:25 +00:00
nickysn
c2305809dc + added an i8086-embedded target support to the compiler (RTL and makefile
support are not done yet)

git-svn-id: trunk@33999 -
2016-06-17 19:15:24 +00:00
florian
a7516dfb50 * fix modification information of VCOMISS and VCOMISD
git-svn-id: trunk@33874 -
2016-06-01 19:58:43 +00:00
nickysn
c78f406d99 + implemented proper stack checking for the i8086
git-svn-id: trunk@33787 -
2016-05-24 23:57:47 +00:00
nickysn
ce66597df8 * handle classrefdefs properly, according to the memory model in i8086's
thlcgobj.getaddressregister. This should fix several regressions in the
  compact, large and huge memory models after r33591

git-svn-id: trunk@33637 -
2016-05-03 15:11:32 +00:00
florian
0c13f3ce3e * fix modification information for vand*
git-svn-id: trunk@33593 -
2016-05-01 12:00:25 +00:00
florian
406e3c4ac1 + support xgetbv instruction, resolves issue #29958
git-svn-id: trunk@33418 -
2016-04-03 20:53:10 +00:00