This slightly changes the semantics of RegUsedAfterInstruction.
We now check if the `current value` of the register will be used later.
It will do `the right thing` for all the normal use cases.
git-svn-id: trunk@21519 -
The loop checked for the wrong instruction for .opcode = A_STR. Making
the whole optimizer non functional but at least not destructive.
git-svn-id: trunk@21508 -
This optimizer folds shift/roll operations into following data
instructions.
It will change code like:
mov r0, r0, lsl #16
add r1, r0, r1
into
add r1, r1, r0, lsl #16
Source registers will be reordered when necessary, also SUB/SBC will be
replaced with RSB/RSC and vice versa when reordering is required.
It could be expanded to support more operations like LDR/STR.
git-svn-id: trunk@21507 -
This changes the ARM Peephole optimizer RedundantMovProcess to also
recognize and modify something like the following sequence.
mov r0, r1
mov r0, r0, lsl #8
this would be changed into
mov r0, r1, lsl #8
git-svn-id: trunk@21506 -
- Support MLA and MUL in DataMov2Data
- SMLAL and UMLAL are also reading from oper[0]
- UMLAL, UMULL, SMLAL and SMULL are writing to oper[1]
git-svn-id: trunk@21421 -
Improve ARM-Peephole Optimizers
1.) Introduce a ARM-specific RegUsedAfterInstruction which analyzes
instructions and reg allocation information to see if a register is
really needed afterwards to decide if some special optimizations can be
done.
2.) Introduce "RemoveSuperfluousMove"
This tries to fold mov into a previous Data-Instruction (ADD, ORR, etc)
or LDR-Instruction.
3.) Introduce new Optimizer "DataMov2Data" and modify LdrMov2Ldr to use
RemoveSuperfluousMove
4.) Expand Ldr* and Str* Optimizers to also work on {Ldr,Str}{,b,h}
git-svn-id: trunk@21314 -
* Introduce MatchInstruction and MatchOperand
MatchInstruction allows to match an instruction by condition and
oppostfix. MatchOperand checks if an operand is a register and matches
another operand. In the future this could be overloaded with other
versions not only accepting TRegister.
* Optimize cmp,moveq,movne sequence on ARM
This patch implements an peephole optimizer for the following sequence:
cmp reg,const1
movne reg,const2
moveq reg,const1
* Small improvements to the ARM peephole optimizer
Most instructions in the ARM ISA have taicpu(p).oper[0]^.typ = top_reg
as the only option, so there is no need to check for it if we're
looking at those instructions.
* Remove redundant mov instructions on ARM
This is an addition to the ARM PeepHole Optimizer.
It folds code like this:
mov reg1, reg2
add reg1, reg1, (const|reg)
git-svn-id: trunk@21024 -
* remove unnecessary ldr after str to the same memoy location, however, to do this optimization safely, we should add support for volatile variables
git-svn-id: trunk@20399 -
-- Zusammenführen der Unterschiede zwischen Projektarchiv-URLs in ».«:
U rtl/arm/setjump.inc
A rtl/arm/thumb2.inc
U rtl/arm/divide.inc
A rtl/embedded/arm/stm32f103.pp
U rtl/inc/system.inc
U compiler/alpha/cgcpu.pas
U compiler/sparc/cgcpu.pas
U compiler/i386/cgcpu.pas
U compiler/ncgld.pas
U compiler/powerpc/cgcpu.pas
U compiler/avr/cgcpu.pas
U compiler/aggas.pas
U compiler/powerpc64/cgcpu.pas
U compiler/x86_64/cgcpu.pas
U compiler/cgobj.pas
U compiler/psystem.pas
U compiler/aasmtai.pas
U compiler/m68k/cgcpu.pas
U compiler/ncgutil.pas
U compiler/rautils.pas
U compiler/arm/raarmgas.pas
U compiler/arm/armatts.inc
U compiler/arm/cgcpu.pas
U compiler/arm/armins.dat
U compiler/arm/rgcpu.pas
U compiler/arm/cpubase.pas
U compiler/arm/agarmgas.pas
U compiler/arm/cpuinfo.pas
U compiler/arm/armop.inc
U compiler/arm/narmadd.pas
U compiler/arm/aoptcpu.pas
U compiler/arm/armatt.inc
U compiler/arm/aasmcpu.pas
U compiler/systems/t_embed.pas
U compiler/psub.pas
U compiler/options.pas
git-svn-id: trunk@13801 -
