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102 Commits

Author SHA1 Message Date
florian
1d629270ca * RiscV64: fix abs(<longint>) 2024-10-14 21:10:10 +02:00
florian
2cfb790eb7 * apply OptPass1FOP to FCVT.*.* 2024-10-13 23:18:38 +02:00
florian
c83a047dda * extend use of OptPass1FOP 2024-10-11 23:14:03 +02:00
florian
28e1daa8e1 * apply OptPass1FOP to more opcodes 2024-10-06 22:48:00 +02:00
florian
fe4f121721 * generalize FOpFsgnj02FOp optimization 2024-10-05 22:32:17 +02:00
florian
477b9ad556 + RiscV: FOp.sFsgnj.s02FOp.s optimization 2024-10-04 22:57:26 +02:00
florian
683b566cb7 * improve RiscV assembler optimizer 2024-10-03 22:56:47 +02:00
florian
42f15792ec + first batch of instructions added for Addi0Op2Op 2024-10-02 23:12:31 +02:00
florian
584e49c6a2 * Addi0Op2Op has to consider both operands 2024-10-01 22:52:43 +02:00
florian
e9fa0510d0 * RiscV: extend Addi0Op2Op 2024-09-30 22:48:18 +02:00
florian
b667be825e + RiscV: Addi0Op2Op optimization 2024-09-29 23:15:22 +02:00
florian
f356d8cc51 * fix RiscV32 compilation 2024-09-25 22:25:01 +02:00
florian
2123c59941 + RiscV: AndiAddwi02Andi optimization 2024-09-24 22:33:53 +02:00
florian
7c023d33d0 * RiscV: fix AndiAndi2Andi optimization 2024-09-24 22:21:32 +02:00
florian
8dcf4e62b7 * FCVT.W.D returns only a 32 bit int 2024-08-17 18:24:16 +02:00
florian
081af9a892 * overleft cosmetics 2024-08-13 22:54:19 +02:00
florian
6ef37d999a + Risc-V: instructions of B extension 2024-08-12 21:51:22 +02:00
florian
f1a173bdf6 * improve Risv-V optimizer 2024-08-10 21:57:55 +02:00
florian
d4816d12f7 * Risc-V 32 has also a GC variant 2024-08-08 22:58:47 +02:00
florian
1ecc880fc8 + cpu type RV64GC 2024-08-07 22:53:10 +02:00
florian
23dec631f5 + Risc-V: apply OptPass1OP to more operations 2024-08-05 22:37:59 +02:00
florian
cc2406ad74 * factor out TRVCpuAsmOptimizer.OptPass1Add 2024-08-03 21:55:41 +02:00
florian
8708144c50 + RiscV: AndiAndi2Andi 2024-08-02 22:15:37 +02:00
florian
80febbd8cf * Risc-V: use OptPass1OP more 2024-08-01 22:24:07 +02:00
florian
a4242e60b2 + Risc-V 32: apply OptPass1OP also on ADD 2024-07-28 22:56:52 +02:00
florian
657e4bf838 * more use of OptPass1OP 2024-07-28 21:39:06 +02:00
florian
9c81c4a5fa * apply OptPass1OP to more instructions 2024-07-28 16:58:49 +02:00
florian
1c96bf5d30 + S*LI x,x,0 to nop optimization 2024-07-27 21:06:49 +02:00
florian
c81f10bfbd + apply OptPass1OP also to SRL/SLL 
* fix commit
 2024-07-27 21:00:03 +02:00
florian
39f7172ee8 * do no generated debug comment in assembler output of RiscV if not requested 2024-05-25 20:16:42 +02:00
florian
a736a4bba7 + set pi_do_call on RiscV as well if we check for fpu exceptions 2024-02-16 22:48:14 +01:00
florian
a71cc71585 + function needs_check_for_fpu_exceptions to unify fpu exception handling 2024-02-13 17:42:21 +01:00
Interferon
8382c6f586 Added generic WCH32Vx RISC-V processor types using memory size suffixes 
Modified low-level startup code for RISCV32 embedded microcontrollers to
allow user code override of reset handlers for non-power-up reset events
as well as enabling user code override handlers for all 255 possible
interrupt vectors.
Separated out the low-level startup memory init into a callable procedure
to allow users that have caught reset events to init memory again if needed.

Signed-off-by: Interferon <brspm2@pinnaclesimulation.com>
 2023-08-26 22:12:00 +02:00
Pierre Muller
87e4931489 Fix fullcycle compilation error due to -Sew option 
Add 'else' branch to 'case' keyword construct
  for the setting of ABI in riscv32 assembler call.
  Do the same for riscv64 assembler call.
 2023-06-14 08:19:06 +02:00
Pierre Muller
0d256f517f Set defualt riscv32 linux abi to abi_riscv_ipl32 2023-06-13 19:39:55 +00:00
florian
0e05e908d5 riscv32-freertos: 
* unit name fixed
 * linker script fixed
 * assembler supports dwarf
 2023-02-09 21:29:06 +01:00
florian
bedd4edc72 + first work for esp32-c3 support 2023-01-28 21:28:19 +01:00
Pierre Muller
49ddf159b2 Fix internalerror generated with riscv32 compiler. 
Fix
  Compiling ./fcl-passrc/src/pscanner.pp
  pscanner.pp(2512,40) Fatal: Internal error 2006010801
  error generated for riscv32-linux target after commit #c83e6c34
  by correcting expectloc for riscv32 for 64-bit comparisons.
  Add a small test.
 2022-10-25 18:42:14 +02:00
florian
e66378ee59 * RiscV: generate mret only for FreeRTOS and Embedded 2022-07-20 22:16:19 +02:00
florian
a16f35dcb1 + support RV32E Extension 2022-07-17 22:14:13 +02:00
Jeppe
f5cf8956c5 riscv: Merge stack code, fix interrupted code 
- Stack pointer is kept below register save area. This ensures that
registers are not overwritten by interrupt handlers.
- RV32 and 64 code is merged to base class.
 2022-07-02 15:07:42 +02:00
florian
a05aa25aad * Risc-V: allow also register aliases in register modification lists after asm blocks, last part to resolve #39738 2022-06-03 22:54:18 +02:00
florian
ea659cbc20 * "fast lane" code and comment fixed 2022-06-02 22:47:58 +02:00
florian
f1b166d6b8 * zero is a valid Risc-V register alias 2022-06-01 22:34:51 +02:00
florian
ec3a04da9b + forgotten pseudo-instructions added 2022-06-01 22:31:26 +02:00
florian
eaeb8b70ff + added Risc-V register information file generation to the compiler Makefile 
* more stringent naming of register file information for Risc-V
 2022-05-31 22:38:30 +02:00
florian
ae457a18ad * unified Risc-V 32 and 64 register data file 2022-05-30 21:10:34 +02:00
florian
4556cb35d1 + completed Risc-V 64 pseudo instructions 
* typo fixed
 2022-05-28 21:22:11 +02:00
florian
6a00f9f403 * unified Risc-V 32 and 64 cpubase.pas 2022-05-28 21:15:53 +02:00
florian
09587d0c1b * standard Risc-V pseudo instructions for Risc-V 32 completed 2022-05-28 20:47:58 +02:00