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342 Commits

Author SHA1 Message Date
florian
413beee9ae -- Zusammenführen von r42652 bis r42673 in ».«: 
U    compiler/x86/aasmcpu.pas
-- Aufzeichnung der Informationen für Zusammenführung von r42652 bis r42673 in ».«:
 U   .

git-svn-id: trunk@42674 -
 2019-08-13 08:54:47 +00:00
tg74
ad791e8e34 bugfix error with avx-memory-parameter OT_MEM128,OT_MEM256,OT_MEM512 
git-svn-id: branches/tg74/avx512@42667 -
 2019-08-12 20:59:53 +00:00
florian
5947143d8f * intel asm reader: try to read avx512 extensions only if the instruction supports them 
* cleanup

git-svn-id: trunk@42656 -
 2019-08-12 10:46:19 +00:00
florian
4c9a0403f4 * compilation on i386 fixed 
git-svn-id: trunk@42655 -
 2019-08-11 19:35:34 +00:00
florian
f883dd6dbb Synchronized with trunk, part 2 (make all works, avx-512 support not yet tested, no regression testing yet) 
git-svn-id: branches/tg74/avx512@42643 -
 2019-08-10 19:38:35 +00:00
florian
746bfced25 Synchronized with trunk, part 1 (only make cycle tested, make all is broken, avx-512 support not yet tested 
git-svn-id: branches/tg74/avx512@42642 -
 2019-08-10 13:53:20 +00:00
Jonas Maebe
281b3ad276 * fix case completeness and unreachable code warnings in compiler that would 
be introduced by the next commit

git-svn-id: trunk@42046 -
 2019-05-12 14:29:03 +00:00
florian
4f0da5fcc3 + patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799 
+ avxopcodes tests also movbe and pclmulqdq

git-svn-id: trunk@40951 -
 2019-01-20 18:50:12 +00:00
florian
72416edcc4 + support for tlsm_general on i386-linux 
git-svn-id: trunk@40281 -
 2018-11-11 17:32:20 +00:00
yury
4357caaad8 * Removed unused local vars. 
git-svn-id: trunk@40183 -
 2018-11-02 18:44:29 +00:00
florian
cdce68451a - x86 align does not use a register anymore, code removed 
git-svn-id: trunk@40157 -
 2018-11-01 20:49:15 +00:00
tg74
60a75a2277 delete testcode 
git-svn-id: branches/tg74/avx512@39936 -
 2018-10-15 10:46:41 +00:00
tg74
1ef9cc01e6 avx512 disp8*N 
git-svn-id: branches/tg74/avx512@39909 -
 2018-10-09 21:19:52 +00:00
tg74
fba72b280b avx512 broadcast vcvt...,vfpclass... 
git-svn-id: branches/tg74/avx512@39778 -
 2018-09-19 15:28:15 +00:00
tg74
4265f4d6a5 avx512 broadcast for special opcodes vfpclass.., vcvt... 
git-svn-id: branches/tg74/avx512@39768 -
 2018-09-19 06:25:42 +00:00
tg74
3759eac608 bugfix avx512 add ZMMReg for gather/scatter in intelOS32 
git-svn-id: branches/tg74/avx512@39741 -
 2018-09-12 06:11:44 +00:00
tg74
8b9d7be8e5 bugfix OS32 
git-svn-id: branches/tg74/avx512@39719 -
 2018-09-10 06:18:48 +00:00
tg74
1d9cbb4dcb new AVX512 opcodes 
git-svn-id: branches/tg74/avx512@39705 -
 2018-09-03 05:40:44 +00:00
tg74
5e1dc1a807 bugfix for test tasm9 32bit 
git-svn-id: branches/tg74/avx512@39695 -
 2018-09-01 08:26:18 +00:00
tg74
6f64177c6a bugfix avx512 OS32bit EVEX-coding 
git-svn-id: branches/tg74/avx512@39661 -
 2018-08-21 22:12:36 +00:00
tg74
29690162b8 bugfix OS32 
git-svn-id: branches/tg74/avx512@39650 -
 2018-08-19 18:41:45 +00:00
tg74
7c5cefad36 bugfix OS32 
git-svn-id: branches/tg74/avx512@39648 -
 2018-08-19 16:35:23 +00:00
tg74
7b8715184a bugfix OS32 
git-svn-id: branches/tg74/avx512@39647 -
 2018-08-19 16:31:09 +00:00
tg74
2b1da37d66 new avx512 instructions and bugfixes avx512 
git-svn-id: branches/tg74/avx512@39636 -
 2018-08-19 10:18:32 +00:00
tg74
867d145e50 support vector operand bcst,{sae},{er} + k-register 
git-svn-id: branches/tg74/avx512@39457 -
 2018-07-16 17:06:57 +00:00
tg74
4dc5442fa5 support vector operand writemask,zeroflag 
git-svn-id: branches/tg74/avx512@39359 -
 2018-07-02 20:20:03 +00:00
tg74
31e4d4ef5e AVX512 support for MMRegister xmm16..31 and ymm16..31, zmm0..31, vpaddsb support AVX512 
git-svn-id: branches/tg74/avx512@39196 -
 2018-06-08 06:53:35 +00:00
marco
f0042a4719 * vcmppd hardcoded primitives like vcmpeqpd. 
* required increasing maxinfolen to 9 

git-svn-id: trunk@38404 -
 2018-03-03 23:32:54 +00:00
florian
f66a91499d * FPC uses meanwhile more mov instructions, so extended taicpu.is_same_reg_move to support them 
git-svn-id: trunk@38264 -
 2018-02-17 09:45:19 +00:00
florian
31f78ea2b6 + implementation of the vectorcall calling convention by J. Gareth Moreton 
+ tests

git-svn-id: trunk@38206 -
 2018-02-11 17:50:37 +00:00
florian
e6a6938787 * make fpu/mmx/xmm/ymm registers numbers instead of flags to have enough space for zmm/bnd/k registers 
git-svn-id: trunk@38116 -
 2018-02-04 20:29:41 +00:00
nickysn
c464f7fa56 * fixed the SEG inline asm directive when used with 32-bit registers on the i8086 target 
git-svn-id: trunk@37613 -
 2017-11-22 15:04:30 +00:00
nickysn
8a0d8f025b * fixed another i8086 inline asm 32-bit constant bug (e.g. in 'or eax, 80000001h') 
git-svn-id: trunk@37521 -
 2017-10-25 19:38:37 +00:00
nickysn
325e66287c * fix for inline asm of instructions with 32-bit constant operands on i8086 
git-svn-id: trunk@37519 -
 2017-10-25 18:03:22 +00:00
nickysn
d7e4b50068 + also optimize x86_64 references by switching [rbp+reg64] to [reg64+rbp], 
[r13+reg64] to [reg64+r13] and [r13d+reg32] to [reg32+r13d]

git-svn-id: trunk@37516 -
 2017-10-24 16:18:43 +00:00
nickysn
5ae32a0ec5 + always do the x86_64 reference optimizations as if SS=DS, because the CPU 
basically ignores these segments in long mode

git-svn-id: trunk@37515 -
 2017-10-24 15:38:59 +00:00
nickysn
875339993f * strip segment overrides, for segments, which should be equal in the current 
model to the default segment of the reference in optimize_ref, when
  inlineasm=false

git-svn-id: trunk@37511 -
 2017-10-23 15:51:33 +00:00
nickysn
80226e3af4 + added an optimization pass, that optimizes x86 references 
git-svn-id: trunk@37494 -
 2017-10-20 15:55:55 +00:00
nickysn
67a0e9bdae + added x86 helper function get_default_segment_of_ref, which returns the 
default segment base for the ref, in case there's no segment override
* in the internal assembler, use get_default_segment_of_ref to strip redundant
  prefixes, instead of always assuming all refs are DS-based

git-svn-id: trunk@37486 -
 2017-10-18 14:24:58 +00:00
nickysn
6f2e64ff90 + added function get_ref_address_size 
git-svn-id: trunk@37470 -
 2017-10-16 14:13:03 +00:00
nickysn
b0653a6313 + added functions is_32_bit_ref and is_64_bit_ref, similar to is_16_bit_ref 
* taicpu.needaddrprefix now uses is_32_bit_ref on x86_64
* is_16/32/64_bit_ref made part of the aasmcpu unit interface, so they can be
  used elsewhere (e.g. in the inline assembler readers)

git-svn-id: trunk@37469 -
 2017-10-16 14:05:06 +00:00
nickysn
2b6e5d817e * changed the parameter of is_16_bit_ref to be a treference, instead of toper 
git-svn-id: trunk@37463 -
 2017-10-16 00:30:26 +00:00
nickysn
baf492c7a5 + another helper function: x86_parameterized_string_op_param_count 
* when generating x86 code for parameterized string instructions with the
  internal object writer, don't rely on the destination operand being [(r/e)di]
  when determining the segment prefix, because when using intel syntax, source
  and destination can be anything (only the operand size, the address size and
  the source segment is taken into account)

git-svn-id: trunk@37452 -
 2017-10-12 16:07:15 +00:00
nickysn
0fb79946a5 + added support for the parameterized versions of the x86 string instructions 
(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
  and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
  is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
  with the 186+ 'ins' instruction.

git-svn-id: trunk@37446 -
 2017-10-12 00:07:02 +00:00
nickysn
92a52a9f4d + implemented support for instructions with non-native address size on i8086 
(16-bit and 32-bit), i386 (16-bit and 32-bit) and x86_64 (32-bit and 64-bit).
  Known bug: 32-bit addresses with an offset have their offset truncated to its
  low 16-bits on i8086

git-svn-id: trunk@37409 -
 2017-10-06 15:27:14 +00:00
nickysn
8589b946fc * different versions (behind cpu specific ifdefs) of process_ea_ref renamed 
process_ea_ref_64_32, process_ea_ref_32 and process_ea_ref_16, indicating
  the address size they support; this is done, so that in the future, we can
  mix them all on the same x86 architecture and support multiple address sizes

git-svn-id: trunk@37407 -
 2017-10-05 22:15:26 +00:00
nickysn
31c9214884 * replaced R_SUBADDR with the appropriate size (R_SUBW, R_SUBD or R_SUBQ) in 
the cpu specific process_ea_ref function

git-svn-id: trunk@37400 -
 2017-10-05 20:39:32 +00:00
nickysn
e701fa8de1 * converted the x86 instruction flags to a set, so they can be extended more 
easily and so that all the values are now available to the compiler
  (previously, there were several, which were mapped to the same value and thus
  were only used to make x86ins.dat easier to read)

git-svn-id: trunk@37299 -
 2017-09-21 15:48:27 +00:00
florian
1ffdf02b94 + Ch_*Op4 
+ op_const_reg_reg_reg

git-svn-id: trunk@36279 -
 2017-05-21 11:12:55 +00:00
florian
b1dff29cbf * removed unused units 
git-svn-id: trunk@36165 -
 2017-05-09 19:53:14 +00:00
nickysn
0c244046a9 * proper register change info for the movs,cmps and scas x86 string instructions 
(movsd still todo, because of the overlap with the sse2 instruction)

git-svn-id: trunk@35929 -
 2017-04-23 21:30:25 +00:00
nickysn
1d34e96064 + added x86 instruction flag Ch_RFLAGScc, indicating instructions that read 
specific bits from the flags register, according to their condition (used by
  Jcc/SETcc/CMOVcc)

git-svn-id: trunk@35907 -
 2017-04-22 22:07:05 +00:00
nickysn
1146b7c12c + added detailed information for individual flag bits use for most x86 
instructions. Not used by the compiler yet, but may allow more
  optimizations in the future.

git-svn-id: trunk@35882 -
 2017-04-21 23:03:33 +00:00
nickysn
869f395a31 + added knowledge to the compiler for the x86 instructions, that don't read 
their input registers, in case both parameters are the same register (e.g.
  xor eax, eax; sub eax, eax; etc.)

git-svn-id: trunk@35861 -
 2017-04-20 15:11:56 +00:00
nickysn
9303a8f61a * changed the x86 TInsProp.Ch structure from a 3-element array to a pascal set; 
this removes the limit of 3 Ch_XXX flags per instruction (thus allowing adding
  more precise flags, e.g. for tracking only certain bits of the flags register,
  etc.) and avoids the ugliness of having the Ch_None filler, which makes
  x86ins.dat less readable.

git-svn-id: trunk@35850 -
 2017-04-19 16:48:35 +00:00
nickysn
189e49998c * fixes to the x86 instruction flags tracking attributes: 
* AAA and AAS also read flags (AF)
  * CMC reads and writes flags (it inverts CF)
  * CMPSx and SCASx write flags
  * CMPSx, SCASx, LODSx, STOSx, MOVSx read the direction flag
  * NOT doesn't affect flags
  * REP isn't affected by and doesn't affect flags
  * REPE/REPNE/REPZ/REPNZ/REPC/REPNC don't write flags, only read them
  * ROL and ROR don't read flags
  * SAL doesn't read flags
  * SHLD and SHRD don't read flags

git-svn-id: trunk@35849 -
 2017-04-19 15:42:50 +00:00
nickysn
3d28878210 + added taicpu.op_reg_reg_ref() constructor for x86, in order to support the 
shld/shrd [ref],reg,CL instructions

git-svn-id: trunk@35832 -
 2017-04-18 12:47:57 +00:00
Jonas Maebe
a25ebbba3e + added volatility information to all memory references 
o separate information for reading and writing, because e.g. in a
     try-block, only the writes to local variables and parameters are
     volatile (they have to be committed immediately in case the next
     instruction causes an exception)
   o for now, only references to absolute memory addresses are marked
     as volatile
   o the volatily information is (should be) properly maintained throughout
     all code generators for all archictures with this patch
   o no optimizers or other compiler infrastructure uses the volatility
     information yet
   o this functionality is not (yet) exposed at the language level, it
     is only for internal code generator use right now

git-svn-id: trunk@34996 -
 2016-11-27 18:17:37 +00:00
sergei
b5660401fe * Some cleanup for AVX part of internal assembler. Functionality is not changed. 
git-svn-id: trunk@34948 -
 2016-11-21 07:49:43 +00:00
sergei
ebe134febc * Fixed memory reference size for MOVSS instruction, Mantis #29954. 
git-svn-id: trunk@34943 -
 2016-11-21 03:31:25 +00:00
sergei
edf943a4f6 * Changed memory operand size for VMOVSS instruction to 32 bits, Mantis #29957. 
git-svn-id: trunk@34918 -
 2016-11-18 23:37:01 +00:00
florian
56252d59f0 + support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933 
git-svn-id: trunk@34917 -
 2016-11-18 20:19:39 +00:00
pierre
38f751573a Copy TExternChain type and AddSymbol procedure to unit aasmcpu from agx86nsm unit 
git-svn-id: trunk@34079 -
 2016-07-06 06:55:31 +00:00
florian
ec92bc3390 * case of identifiers fixed 
* x86-64 uses also the mov $0,... -> xor optimization

git-svn-id: trunk@33553 -
 2016-04-24 20:01:43 +00:00
florian
406e3c4ac1 + support xgetbv instruction, resolves issue #29958 
git-svn-id: trunk@33418 -
 2016-04-03 20:53:10 +00:00
florian
8d5cc3dfa4 * (extended and modified) patch by Emelyanov Roman to add suport of RDRAND, RDSEED and TSX instructions set, resolves issue #29893. 
In comparison with the original patch, support for a i386 has been added as well as a test program. 
  Further, a small issue with xbegin has been fixed

git-svn-id: trunk@33375 -
 2016-03-28 19:08:13 +00:00
nickysn
b562bcfdbd * fixed the alignment filler in code sections on i8086 to always use nops, 
instead of using the optimized instructions for 386+, which assume also a
  32-bit address and operand size, so they didn't work even on a 386+ in real
  mode

git-svn-id: trunk@33371 -
 2016-03-28 15:04:28 +00:00
nickysn
cf3230b100 - removed IF_CENTAUR and replaced it with IF_CYRIX. Rationale: only 3 Centaur - 
specific instructions were marked as CENTAUR, all the others were marked
  CYRIX, so it wasn't an accurate flag at all

git-svn-id: trunk@33326 -
 2016-03-25 17:01:11 +00:00
nickysn
9a2f5e01d7 + added range checking for the immediate operand of NEC V20/V30's instructions CLR1, SET1, NOT1 and TEST1 
git-svn-id: trunk@33322 -
 2016-03-24 16:05:11 +00:00
nickysn
0be6d062ac + added range checking for the imm4 operand of NEC V20/V30's instructions 
'EXT reg8,imm4' and 'INS reg8,imm4'

git-svn-id: trunk@33321 -
 2016-03-24 15:45:23 +00:00
nickysn
a376229d80 - removed IF_CYRIX and IF_AMD from the TODO list of instructions, that we're 
supposed to handle in the i8086 internal asm instruction level check, because
  these two flags are no longer part of the IF_PLEVEL mask, after r33316

git-svn-id: trunk@33318 -
 2016-03-23 15:24:59 +00:00
nickysn
5f87ac5d47 + added 486 to the list of supported CPUs on the i8086 and i386 targets 
git-svn-id: trunk@33317 -
 2016-03-23 15:07:56 +00:00
nickysn
867a4881ba * changed the codes of the IF_CYRIX and IF_AMD instruction flags, to avoid 
messing up the other Intel-compatible processor flag, they're used with

git-svn-id: trunk@33316 -
 2016-03-23 14:00:48 +00:00
nickysn
c061a98e93 * made the i8086 internal assembler cpu instruction set checking follow the 
asd_cpu directive (and thus, respect the {$asmcpu XXX} directive)

git-svn-id: trunk@33141 -
 2016-03-02 01:03:52 +00:00
Jonas Maebe
53052f26a0 * changed output parameter of process_ea_ref() from "out" to "var", as it is 
already partially initialised by its caller (part of mantis #29439)

git-svn-id: trunk@32968 -
 2016-01-18 22:20:26 +00:00
nickysn
439ab331e9 * factored out some of the duplicated (between x86 targets) parts of process_ea() to a common function 
git-svn-id: trunk@32940 -
 2016-01-14 18:00:37 +00:00
nickysn
db5e67c3fe + introduced a new type TRelocDataInt for use as the 'data' parameter for 
TObjData.writeReloc; on i8086 it was changed to longint to allow using 32-bit
  relocations
+ added support for writing 32-bit OMF relocations

git-svn-id: trunk@32936 -
 2016-01-13 17:57:36 +00:00
nickysn
d4c21cf13a * also check for 386+ when emitting a reference with a fs: or gs: prefix 
git-svn-id: trunk@32926 -
 2016-01-11 16:30:06 +00:00
nickysn
ef9504ffd7 * made the \325 x86 prefix to generate a 0x66 prefix on i8086, thus fixing many 
32-bit instructions on i8086, when using the internal obj writer

git-svn-id: trunk@32890 -
 2016-01-08 17:20:37 +00:00
nickysn
e6ac1a4af5 + added check for the compatibility of each instruction with the selected target 
cpu in the i8086's internal obj writer

git-svn-id: trunk@32888 -
 2016-01-08 16:44:28 +00:00
nickysn
a508f9e5d3 + added check if the selected cpu is 386+ when writing a 66h or 67h prefix in 
the i8086 internal object writer. This allows weeding out spurious 386
  instructions, as is similarly done by NASM when using it as an external
  assembler.

git-svn-id: trunk@32871 -
 2016-01-07 15:40:32 +00:00
nickysn
22b6e00147 * extracted the writing of 0x66 and 0x67 prefixes in the x86 internal assembler 
to local procedures write0x66prefix and write0x67prefix

git-svn-id: trunk@32869 -
 2016-01-07 14:18:14 +00:00
nickysn
78362ed6ae * RELOC_ABSOLUTE32 made different than RELOC_ABSOLUTE on i8086 (and fixed all 
the i8086 bugs, related to code that assumes that they are the same)
+ also added RELOC_RELATIVE32 on i8086
* RELOC_ABSOLUTE32 and RELOC_RELATIVE32 are not yet implemented in the OMF
  object writer and linker (and currently produce an internal error), but will
  be implemented in the future, as the OMF format supports both 16-bit and
  32-bit relocations

git-svn-id: trunk@32311 -
 2015-11-13 15:56:26 +00:00
yury
862348c317 * Keep the GOT offset in a virtual register for i386 non-darwin platforms. 
It fixes PIC code generation with GOT for i386 with enabled optimizations. Bugs #28667, #28668. 
  Prior the fix I have not been able to compile even RTL with -O2 due to not enough free registers, since EBX is reserved for GOT.

  It can be further optimized to teach register allocator to not spill the GOT register if possible.
  

git-svn-id: trunk@32020 -
 2015-10-12 08:02:56 +00:00
nickysn
1487236f29 + support addr_fardataseg references in the internal asm writer 
git-svn-id: trunk@31511 -
 2015-09-04 14:33:48 +00:00
nickysn
e9c790f4eb + support 'SEG' in the i8086 inline assembler 
git-svn-id: trunk@31428 -
 2015-08-26 15:57:44 +00:00
nickysn
0da38dbc79 + implemented support for the 'dgroup' (addr_dgroup) relocation type in the omf 
internal object writer

git-svn-id: trunk@30800 -
 2015-05-04 17:07:19 +00:00
nickysn
25a834087e + choose the correct version of "Jcc near" to use on i8086 (386+ or 8086+) 
depending on the specified target cpu type
+ support the \60..\62 magic codes on i8086 in the internal asm writer

git-svn-id: trunk@30613 -
 2015-04-16 19:49:22 +00:00
nickysn
bfd5670cc8 + support new magic code \23 in the internal asm writer - same as \13, but with 
the condition inverted; this will be used to simulate near conditional jumps
  on processors earlier than 386 (i.e. "Jcc near target" will be encoded as
  "JNcc short +3; JMP target")

git-svn-id: trunk@30611 -
 2015-04-16 16:53:48 +00:00
nickysn
955c29618a + support far calls and jumps in the internal asm writer 
git-svn-id: trunk@30601 -
 2015-04-15 00:12:40 +00:00
nickysn
a7e059c875 + support segment relocations in the omf writer 
git-svn-id: trunk@30600 -
 2015-04-14 22:46:01 +00:00
nickysn
f5ddd351fe * allow use of the imm8 form of 16-bit instructions on i8086 
git-svn-id: trunk@30594 -
 2015-04-14 19:14:47 +00:00
nickysn
bd460eec43 * emit 16-bit addresses on i8086 for asm codes &64..&66 in the internal asm 
git-svn-id: trunk@30580 -
 2015-04-13 22:13:15 +00:00
nickysn
22fb1a3e7e * converted all the magic nasm codes in the x86 internal asm writer from decimal 
to octal in the compiler source, so they match the strings in x86ins.dat

git-svn-id: trunk@30566 -
 2015-04-13 01:13:39 +00:00
nickysn
fe30b53e95 * use 16-bit operand types for call/jmp immediate on i8086 in taicpu.create_ot 
git-svn-id: trunk@30563 -
 2015-04-12 23:53:15 +00:00
nickysn
a25a906d56 * i8086 internal asm fixes for the 0324 and 0361 asm codes 
git-svn-id: trunk@30562 -
 2015-04-12 22:56:28 +00:00
nickysn
fd9e0d7266 * i8086 binary writer fixes for asm codes 0320..0322 
git-svn-id: trunk@30526 -
 2015-04-09 23:10:47 +00:00
nickysn
db5276af61 * i8086 binary writer fixes for asm codes 0300..0302 
git-svn-id: trunk@30525 -
 2015-04-09 22:56:47 +00:00
nickysn
0aa8e9d829 + i8086 fixes in the binary writer for asm codes 0310 and 0311 
git-svn-id: trunk@30524 -
 2015-04-09 22:47:21 +00:00
nickysn
8597208ed9 * fixed emitting a 66h prefix for push/pop of segment registers on i8086 in the internal asm writer 
git-svn-id: trunk@30523 -
 2015-04-09 22:01:24 +00:00