40307
40309
40314
40319
40322
40324
40326
40377
40378 from trunk to fixes_3_2
------------------------------------------------------------------------
r40277 | pierre | 2018-11-08 20:18:30 +0000 (Thu, 08 Nov 2018) | 1 line
Implement mark_write override for tinilinenode
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--- Merging r40277 into '.':
U compiler/ninl.pas
--- Recording mergeinfo for merge of r40277 into '.':
U .
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r40307 | pierre | 2018-11-13 15:10:21 +0000 (Tue, 13 Nov 2018) | 6 lines
+ Introduce PPC_SUFFIXES, new make variable that lists all ppc suffixes
for all different CPUs supported.
* Use PPC_SUFFIXES in execlean and CPU_clean targets.
* Also delete CPU/bin subbirectory.
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--- Merging r40307 into '.':
U compiler/Makefile
U compiler/Makefile.fpc
--- Recording mergeinfo for merge of r40307 into '.':
G .
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r40309 | pierre | 2018-11-13 15:51:32 +0000 (Tue, 13 Nov 2018) | 1 line
Try to avoid expectloc not set after first pass error for call node
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--- Merging r40309 into '.':
U compiler/ncal.pas
--- Recording mergeinfo for merge of r40309 into '.':
G .
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r40314 | pierre | 2018-11-14 13:13:19 +0000 (Wed, 14 Nov 2018) | 4 lines
* Change first parameter type of function is_continuous_maks to aword type.
Add typecasts where needed to allow for successful compilation of arm-linux target
with -CriotR options when building the compiler.
------------------------------------------------------------------------
--- Merging r40314 into '.':
U compiler/arm/cpubase.pas
U compiler/arm/cgcpu.pas
--- Recording mergeinfo for merge of r40314 into '.':
G .
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r40319 | pierre | 2018-11-15 16:58:40 +0000 (Thu, 15 Nov 2018) | 1 line
Disable range check in m68k:tiscv32 and riscv64 cgcpu units
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--- Merging r40319 into '.':
C compiler/riscv64
U compiler/m68k/cgcpu.pas
C compiler/riscv32
--- Recording mergeinfo for merge of r40319 into '.':
G .
Summary of conflicts:
Tree conflicts: 2
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r40322 | pierre | 2018-11-15 22:01:25 +0000 (Thu, 15 Nov 2018) | 1 line
Also disable range checking in arm/aoptcpu unit
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--- Merging r40322 into '.':
U compiler/arm/aoptcpu.pas
--- Recording mergeinfo for merge of r40322 into '.':
G .
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r40324 | pierre | 2018-11-16 10:27:42 +0000 (Fri, 16 Nov 2018) | 4 lines
* Disable range check for m68k/aoptcpu unit
* Add missing change of var parameter p to next instruction
in TryToOptimizeMove method after instruction removal.
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--- Merging r40324 into '.':
U compiler/m68k/aoptcpu.pas
--- Recording mergeinfo for merge of r40324 into '.':
G .
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r40326 | pierre | 2018-11-16 13:28:26 +0000 (Fri, 16 Nov 2018) | 1 line
Change local variables offsetdec and extraoffset type to ASizeInt
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--- Merging r40326 into '.':
U compiler/ncgmem.pas
--- Recording mergeinfo for merge of r40326 into '.':
G .
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r40377 | pierre | 2018-11-27 10:19:36 +0000 (Tue, 27 Nov 2018) | 1 line
Fix bug report 34605 and add corresponding test
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--- Merging r40377 into '.':
A tests/webtbs/tw34605.pp
U compiler/nutils.pas
--- Recording mergeinfo for merge of r40377 into '.':
G .
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r40378 | pierre | 2018-11-27 10:21:37 +0000 (Tue, 27 Nov 2018) | 1 line
Avoid range errors or overflows on for AVR cpu, when computing address offsets
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--- Merging r40378 into '.':
U compiler/ncgset.pas
U compiler/ngtcon.pas
--- Recording mergeinfo for merge of r40378 into '.':
G .
git-svn-id: branches/fixes_3_2@40716 -
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r39725 | pierre | 2018-09-10 13:28:33 +0000 (Mon, 10 Sep 2018) | 1 line
Add branches for 3.2.0, 3.2.1 and 3.3.1 versions
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--- Merging r39725 into '.':
U tests/utils/testsuite/utests.pp
--- Recording mergeinfo for merge of r39725 into '.':
U .
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r39733 | pierre | 2018-09-11 08:16:56 +0000 (Tue, 11 Sep 2018) | 1 line
sparc64-linux objects recompiled with GCC 7.3.0
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--- Merging r39733 into '.':
U tests/test/cg/obj/readme.txt
U tests/test/cg/obj/linux/sparc64/ctest.o
U tests/test/cg/obj/linux/sparc64/cpptcl1.o
U tests/test/cg/obj/linux/sparc64/cpptcl2.o
U tests/test/cg/obj/linux/sparc64/tcext3.o
U tests/test/cg/obj/linux/sparc64/tcext4.o
U tests/test/cg/obj/linux/sparc64/tcext5.o
U tests/test/cg/obj/linux/sparc64/tcext6.o
--- Recording mergeinfo for merge of r39733 into '.':
G .
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r39808 | pierre | 2018-09-26 09:29:33 +0000 (Wed, 26 Sep 2018) | 1 line
Disable libraries not compiling for jvm-java or jvm-android targets
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--- Merging r39808 into '.':
U packages/fppkg/fpmake.pp
U packages/fcl-base/fpmake.pp
U packages/rtl-extra/fpmake.pp
U packages/hermes/fpmake.pp
U packages/fcl-extra/fpmake.pp
U packages/fcl-db/fpmake.pp
U packages/unzip/fpmake.pp
U packages/odbc/fpmake.pp
U packages/gdbm/fpmake.pp
U packages/pthreads/fpmake.pp
U packages/fcl-json/fpmake.pp
U packages/pcap/fpmake.pp
U packages/numlib/fpmake.pp
U packages/rtl-generics/fpmake.pp
U packages/zlib/fpmake.pp
U packages/paszlib/fpmake.pp
U packages/webidl/fpmake.pp
U packages/regexpr/fpmake.pp
U packages/libgd/fpmake.pp
U packages/fcl-net/fpmake.pp
U packages/fcl-res/fpmake.pp
U packages/libpng/fpmake.pp
U packages/dblib/fpmake.pp
U packages/tcl/fpmake.pp
U packages/openssl/fpmake.pp
U packages/ibase/fpmake.pp
U packages/bzip2/fpmake.pp
U packages/fcl-sdo/fpmake.pp
U packages/fcl-sound/fpmake.pp
U packages/fcl-passrc/fpmake.pp
U packages/fcl-stl/fpmake.pp
U packages/libmicrohttpd/fpmake.pp
U packages/mysql/fpmake.pp
U packages/postgres/fpmake.pp
U packages/httpd22/fpmake.pp
U packages/httpd24/fpmake.pp
U packages/rtl-console/fpmake.pp
U packages/sqlite/fpmake.pp
U packages/fftw/fpmake.pp
U packages/fcl-pdf/fpmake.pp
U packages/rtl-objpas/fpmake.pp
U packages/fcl-image/fpmake.pp
U packages/pasjpeg/fpmake.pp
U packages/chm/fpmake.pp
U packages/fcl-registry/fpmake.pp
U packages/libtar/fpmake.pp
U packages/symbolic/fpmake.pp
U packages/libenet/fpmake.pp
U packages/imagemagick/fpmake.pp
U packages/fcl-xml/fpmake.pp
U packages/oracle/fpmake.pp
U packages/fcl-fpcunit/fpmake.pp
U packages/fcl-js/fpmake.pp
U packages/fcl-async/fpmake.pp
U packages/fcl-process/fpmake.pp
U packages/pastojs/fpmake.pp
U packages/hash/fpmake.pp
U packages/rtl-unicode/fpmake.pp
U packages/fpmkunit/fpmake.pp
--- Recording mergeinfo for merge of r39808 into '.':
G .
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r40027 | pierre | 2018-10-24 21:37:54 +0000 (Wed, 24 Oct 2018) | 1 line
Fix compilation of RTL for watcom target
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--- Merging r40027 into '.':
U compiler/x86/agx86int.pas
--- Recording mergeinfo for merge of r40027 into '.':
G .
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r40028 | pierre | 2018-10-25 06:39:42 +0000 (Thu, 25 Oct 2018) | 1 line
Try to fix compilation error after commit #40027
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--- Merging r40028 into '.':
G compiler/x86/agx86int.pas
--- Recording mergeinfo for merge of r40028 into '.':
G .
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r40102 | pierre | 2018-10-31 09:07:57 +0000 (Wed, 31 Oct 2018) | 1 line
Replace aint (which is a compiler specific type) by ptruint type, which is defined in system unit
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--- Merging r40102 into '.':
U tests/test/tarray5.pp
--- Recording mergeinfo for merge of r40102 into '.':
G .
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r40103 | pierre | 2018-10-31 09:59:45 +0000 (Wed, 31 Oct 2018) | 1 line
Use pdword to avoid range check erro in tentryfile.getdword method
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--- Merging r40103 into '.':
U compiler/entfile.pas
--- Recording mergeinfo for merge of r40103 into '.':
G .
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r40104 | pierre | 2018-10-31 10:21:51 +0000 (Wed, 31 Oct 2018) | 1 line
Use longint type instead of AWord for Initial parameter in CalcExecutionWeigths (to avoid range error for avr compiler)
------------------------------------------------------------------------
@@
begin
Result:=fen_false;
n.allocoptinfo;
<<<<<<< MINE (select with 'mc') (367)
Weight:=PAWord(arg)^;
||||||| ORIGINAL (367)
Weight:=max(PAWord(arg)^,1);
=======
Weight:=max(plongint(arg)^,1);
>>>>>>> THEIRS (select with 'tc') (367)
case n.nodetype of
casen:
begin
--- Merging r40104 into '.':
C compiler/optutils.pas
--- Recording mergeinfo for merge of r40104 into '.':
G .
Summary of conflicts:
Text conflicts: 1
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r40110 | pierre | 2018-10-31 14:51:23 +0000 (Wed, 31 Oct 2018) | 1 line
Avoid range check error in MaskLength evaluation
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--- Merging r40110 into '.':
U compiler/x86/aoptx86.pas
--- Recording mergeinfo for merge of r40110 into '.':
G .
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r40111 | pierre | 2018-10-31 15:47:53 +0000 (Wed, 31 Oct 2018) | 1 line
Complement commit 40104, by changing type of executionweight in toptinfo record and adapt pass_2 code
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--- Merging r40111 into '.':
U compiler/pass_2.pas
U compiler/optbase.pas
--- Recording mergeinfo for merge of r40111 into '.':
G .
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r40112 | pierre | 2018-10-31 15:48:32 +0000 (Wed, 31 Oct 2018) | 1 line
Disable range check completely in arm/cgcpu unit
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--- Merging r40112 into '.':
U compiler/arm/cgcpu.pas
--- Recording mergeinfo for merge of r40112 into '.':
G .
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r40113 | pierre | 2018-10-31 15:49:14 +0000 (Wed, 31 Oct 2018) | 1 line
Avoid overflow in code
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--- Merging r40113 into '.':
U compiler/symdef.pas
--- Recording mergeinfo for merge of r40113 into '.':
G .
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r40114 | pierre | 2018-10-31 15:50:26 +0000 (Wed, 31 Oct 2018) | 1 line
Add explicit rtlclean/rtl targets in fullcycle rule if DOWPOCYCLE is set
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--- Merging r40114 into '.':
U compiler/Makefile.fpc
U compiler/Makefile
--- Recording mergeinfo for merge of r40114 into '.':
G .
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r40120 | pierre | 2018-10-31 23:15:22 +0000 (Wed, 31 Oct 2018) | 1 line
Change RemoveCurrentP parameter type to tai, because GetNextInstruction does not always return a taicpu, adapt code in avr/aoptcpu unit
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--- Merging r40120 into '.':
U compiler/aoptobj.pas
U compiler/avr/aoptcpu.pas
--- Recording mergeinfo for merge of r40120 into '.':
G .
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r40121 | pierre | 2018-10-31 23:16:51 +0000 (Wed, 31 Oct 2018) | 1 line
Add check about tloadnode.symtableentry type before typecast
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--- Merging r40121 into '.':
U compiler/ncal.pas
--- Recording mergeinfo for merge of r40121 into '.':
G .
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r40122 | pierre | 2018-10-31 23:18:09 +0000 (Wed, 31 Oct 2018) | 1 line
Fix typecast in FindRegDeAlloc call
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--- Merging r40122 into '.':
U compiler/arm/aoptcpu.pas
--- Recording mergeinfo for merge of r40122 into '.':
G .
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r40123 | pierre | 2018-10-31 23:19:39 +0000 (Wed, 31 Oct 2018) | 1 line
Remove unneeded typecasts in TryTOptimizeMove
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--- Merging r40123 into '.':
U compiler/m68k/aoptcpu.pas
--- Recording mergeinfo for merge of r40123 into '.':
G .
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r40124 | pierre | 2018-10-31 23:20:29 +0000 (Wed, 31 Oct 2018) | 1 line
Add global range check disable for i8086 cgcpu and x86 nx86add units
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--- Merging r40124 into '.':
U compiler/i8086/cgcpu.pas
U compiler/x86/nx86add.pas
--- Recording mergeinfo for merge of r40124 into '.':
G .
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r40131 | pierre | 2018-11-01 07:01:02 +0000 (Thu, 01 Nov 2018) | 1 line
Remove another wrong typecast when testing that a tai is an instruction
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--- Merging r40131 into '.':
G compiler/m68k/aoptcpu.pas
--- Recording mergeinfo for merge of r40131 into '.':
G .
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r40236 | pierre | 2018-11-06 07:40:31 +0000 (Tue, 06 Nov 2018) | 1 line
Really change extension of hs1 local variable in get_exepath
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--- Merging r40236 into '.':
U compiler/globals.pas
--- Recording mergeinfo for merge of r40236 into '.':
G .
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r40237 | pierre | 2018-11-06 07:41:15 +0000 (Tue, 06 Nov 2018) | 1 line
Disable range checking in rax86int unit
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--- Merging r40237 into '.':
U compiler/x86/rax86int.pas
--- Recording mergeinfo for merge of r40237 into '.':
G .
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r40278 | pierre | 2018-11-08 20:19:54 +0000 (Thu, 08 Nov 2018) | 1 line
Downgrade EXTDEBUG warning to note about zero size temp, as it is used for empty sets
------------------------------------------------------------------------
--- Merging r40278 into '.':
U compiler/tgobj.pas
--- Recording mergeinfo for merge of r40278 into '.':
G .
git-svn-id: branches/fixes_3_2@40624 -
* ARM: Remove preindexing and postindexing for LDR in some cases when removing superfluous MOVs. It fixes crash when calling Format() if rtl is compiled with -O3.
........
* Improved the comment.
........
git-svn-id: branches/fixes_3_2@40588 -
- all reg allocs and PIC labeels before the instruction;
- all reg deallocs and reg syncs after the instruction.
It fixes bug #31135.
git-svn-id: trunk@35545 -
* updated TAOptObj.RegUsedAfterInstruction with the arm implementation and removed the arm specific implementation
* RegLoadedWithNewValue and InstructionLoadsFromReg are now a methods of TAoptBase
* moved RegEndOfLife to TAOptObj
* during this refactoring, fixed also TCpuAsmOptimizer.RegLoadedWithNewValue for arm regarding post/preindexed
memory references: those modify the register but do not load it with a new value in the sense of RegLoadedWithNewValue
git-svn-id: trunk@33000 -
Switched codegeneration of VFPv2 and VFPv3 to use UAL mnemonics and syntax.
Updated VFP code in RTL to use UAL syntax too.
Added preliminary ELF support for ARM.
Added support for linking of WinCE COFF files. Should work for with a standard ARMv4-I target.
git-svn-id: branches/laksen/armiw@29247 -
A more radical approach is to remove them altogether. Tested with i386-win32 (the oldest peephole optimizer), mips-linux (the newest one) and arm-linux (the most complex one) targets. The fallout was limited to two minor issues fixed in r28629 and r28708, respectively.
git-svn-id: trunk@28711 -
StrLdr2StrMov now uses GetNextInstructionUsingRef to find an instruction
which uses the same Reference. In one of our internal testcases it
speeded up a function by 15% as fpc generated a lot of spilling.
git-svn-id: trunk@28344 -
It's the counterpart to GetNextInstructionUsingReg and finds the next
instruction to use the same reference. By default it stops searching
when hitting a store instructions to avoid aliasing issues.
git-svn-id: trunk@28343 -
There was an interference between the load scheduler and then
Str/LdrAdd/Sub2Str/Ldr peephole optimizer.
ldrb r0, [r2]
ldrb r1, [r2, #1]
orr r3, r0, r1
add r2, r2, #2
got changed pre-regalloc to:
ldrb r1, [r2, #1]
ldrb r0, [r2]
orr r3, r0, r1
add r2, r2, #2
and the peephole optimizer collapsed the add into the second ldrd:
ldrb r1, [r2, #1]
ldrb r0, [r2], #2
orr r3, r0, r1
Then the post-peephole optimizer changed that into:
ldrb r0, [r2], #2
ldrb r1, [r2, #1]
orr r3, r0, r1
so r1 got loaded from a modified base-register.
This patch prevents the scheduler from moving an ldr-instruction if it
uses Pre/Post-indexing and the instruction before it uses the
base-register.
git-svn-id: trunk@28284 -
Use UXTH+UXTB instructions instead of two shifts on processors that supports that.
Eliminate internalerror when constant pointers are typecast as arrays.
git-svn-id: trunk@26647 -
The load scheduler does not handle LDRD correctly right now, but it does
not prevent A_LDR with PF_D set from beeing scheduled.
git-svn-id: trunk@26637 -
Some time ago we introduced GetNextInstructionUsingReg, which might
return an instruction a couple of instructions away from our current
location. Most of the code then just returned the new instruction (hp1)
instead of the instruction following p. This could prevent the peephole
optimizer from finding possible optimizations.
git-svn-id: trunk@26605 -
The existing LdrLdr2LdrMov optimizer will generate a lot of
sequences like this:
ldr regA, [...]
mov regB, regA
ldr regB, [regB, ...]
this now gets changed to
ldr regA, [...]
ldr regB, [regA, ...]
this saves an instruction and might open up more possibilities for the load scheduler.
git-svn-id: trunk@26603 -
LDRD and STRD only have the first even numbered register in their instruction operands,
this additional code will also check for the register following it.
Example:
ldrd r0, [r13]
The old code will only detect r0 as in use, not the implicit r1.
git-svn-id: trunk@26602 -
Fixed a bug where ARMv7M targets would not use the DIV instructions.
Moved many size-optimizing Thumb2 peephole optimizations to PostPeepHoleOptsCpu. Previously those optimizations could make it impossible to reuse the shared arm peephole optimizations.
Reenabled a fixed MLA/MLS peephole optimization.
Refactored some FindRegDealloc+regLoadedWithNewValue into RegEndOfLife calls.
Fixed some broken UXTB/UXTH optimizations. Previously they would also match UXT* instructions with ROR shifter ops.
git-svn-id: trunk@26198 -
The previous code deleted the newly inserted instruction instead of the
existing one, which obviously broke code.
Assembly:
mov r0, r0, lsr #23
mov r0, r0, lsr #23
transformed into:
mov r0, r0, lsr #23
expected was:
mov r0, #0
The problem only shows up in the very unlikely case of two LSR/ASR or
two LSL following on each other and having a total shift of more than 31
bits.
This fixes test/opt/tarmshift.pp
I've also removed the {%norun} directive from tarmshift.pp as this test
does only make sense when it also runs.
git-svn-id: trunk@25374 -
