* updated TAOptObj.RegUsedAfterInstruction with the arm implementation and removed the arm specific implementation
* RegLoadedWithNewValue and InstructionLoadsFromReg are now a methods of TAoptBase
* moved RegEndOfLife to TAOptObj
* during this refactoring, fixed also TCpuAsmOptimizer.RegLoadedWithNewValue for arm regarding post/preindexed
memory references: those modify the register but do not load it with a new value in the sense of RegLoadedWithNewValue
git-svn-id: trunk@33000 -
Switched codegeneration of VFPv2 and VFPv3 to use UAL mnemonics and syntax.
Updated VFP code in RTL to use UAL syntax too.
Added preliminary ELF support for ARM.
Added support for linking of WinCE COFF files. Should work for with a standard ARMv4-I target.
git-svn-id: branches/laksen/armiw@29247 -
A more radical approach is to remove them altogether. Tested with i386-win32 (the oldest peephole optimizer), mips-linux (the newest one) and arm-linux (the most complex one) targets. The fallout was limited to two minor issues fixed in r28629 and r28708, respectively.
git-svn-id: trunk@28711 -
StrLdr2StrMov now uses GetNextInstructionUsingRef to find an instruction
which uses the same Reference. In one of our internal testcases it
speeded up a function by 15% as fpc generated a lot of spilling.
git-svn-id: trunk@28344 -
It's the counterpart to GetNextInstructionUsingReg and finds the next
instruction to use the same reference. By default it stops searching
when hitting a store instructions to avoid aliasing issues.
git-svn-id: trunk@28343 -
There was an interference between the load scheduler and then
Str/LdrAdd/Sub2Str/Ldr peephole optimizer.
ldrb r0, [r2]
ldrb r1, [r2, #1]
orr r3, r0, r1
add r2, r2, #2
got changed pre-regalloc to:
ldrb r1, [r2, #1]
ldrb r0, [r2]
orr r3, r0, r1
add r2, r2, #2
and the peephole optimizer collapsed the add into the second ldrd:
ldrb r1, [r2, #1]
ldrb r0, [r2], #2
orr r3, r0, r1
Then the post-peephole optimizer changed that into:
ldrb r0, [r2], #2
ldrb r1, [r2, #1]
orr r3, r0, r1
so r1 got loaded from a modified base-register.
This patch prevents the scheduler from moving an ldr-instruction if it
uses Pre/Post-indexing and the instruction before it uses the
base-register.
git-svn-id: trunk@28284 -
Use UXTH+UXTB instructions instead of two shifts on processors that supports that.
Eliminate internalerror when constant pointers are typecast as arrays.
git-svn-id: trunk@26647 -
The load scheduler does not handle LDRD correctly right now, but it does
not prevent A_LDR with PF_D set from beeing scheduled.
git-svn-id: trunk@26637 -
Some time ago we introduced GetNextInstructionUsingReg, which might
return an instruction a couple of instructions away from our current
location. Most of the code then just returned the new instruction (hp1)
instead of the instruction following p. This could prevent the peephole
optimizer from finding possible optimizations.
git-svn-id: trunk@26605 -
The existing LdrLdr2LdrMov optimizer will generate a lot of
sequences like this:
ldr regA, [...]
mov regB, regA
ldr regB, [regB, ...]
this now gets changed to
ldr regA, [...]
ldr regB, [regA, ...]
this saves an instruction and might open up more possibilities for the load scheduler.
git-svn-id: trunk@26603 -
LDRD and STRD only have the first even numbered register in their instruction operands,
this additional code will also check for the register following it.
Example:
ldrd r0, [r13]
The old code will only detect r0 as in use, not the implicit r1.
git-svn-id: trunk@26602 -
Fixed a bug where ARMv7M targets would not use the DIV instructions.
Moved many size-optimizing Thumb2 peephole optimizations to PostPeepHoleOptsCpu. Previously those optimizations could make it impossible to reuse the shared arm peephole optimizations.
Reenabled a fixed MLA/MLS peephole optimization.
Refactored some FindRegDealloc+regLoadedWithNewValue into RegEndOfLife calls.
Fixed some broken UXTB/UXTH optimizations. Previously they would also match UXT* instructions with ROR shifter ops.
git-svn-id: trunk@26198 -
The previous code deleted the newly inserted instruction instead of the
existing one, which obviously broke code.
Assembly:
mov r0, r0, lsr #23
mov r0, r0, lsr #23
transformed into:
mov r0, r0, lsr #23
expected was:
mov r0, #0
The problem only shows up in the very unlikely case of two LSR/ASR or
two LSL following on each other and having a total shift of more than 31
bits.
This fixes test/opt/tarmshift.pp
I've also removed the {%norun} directive from tarmshift.pp as this test
does only make sense when it also runs.
git-svn-id: trunk@25374 -
The optimizer now juggles around the base and index register if that opens
up the possibility of folding the shift into the instruction.
This can only be done in the case of addressmode=AM_OFFSET, in case of
[AM_POSTINDEXED, AM_PREINDEXED] we can not move the base register, as this
would cause havoc and destruction.
git-svn-id: trunk@24645 -
