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49ddf159b2
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65 Commits

Author SHA1 Message Date
Pierre Muller
49ddf159b2 Fix internalerror generated with riscv32 compiler. 
Fix
  Compiling ./fcl-passrc/src/pscanner.pp
  pscanner.pp(2512,40) Fatal: Internal error 2006010801
  error generated for riscv32-linux target after commit #c83e6c34
  by correcting expectloc for riscv32 for 64-bit comparisons.
  Add a small test.
 2022-10-25 18:42:14 +02:00
florian
e66378ee59 * RiscV: generate mret only for FreeRTOS and Embedded 2022-07-20 22:16:19 +02:00
florian
a16f35dcb1 + support RV32E Extension 2022-07-17 22:14:13 +02:00
Jeppe
f5cf8956c5 riscv: Merge stack code, fix interrupted code 
- Stack pointer is kept below register save area. This ensures that
registers are not overwritten by interrupt handlers.
- RV32 and 64 code is merged to base class.
 2022-07-02 15:07:42 +02:00
florian
a05aa25aad * Risc-V: allow also register aliases in register modification lists after asm blocks, last part to resolve #39738 2022-06-03 22:54:18 +02:00
florian
ea659cbc20 * "fast lane" code and comment fixed 2022-06-02 22:47:58 +02:00
florian
f1b166d6b8 * zero is a valid Risc-V register alias 2022-06-01 22:34:51 +02:00
florian
ec3a04da9b + forgotten pseudo-instructions added 2022-06-01 22:31:26 +02:00
florian
eaeb8b70ff + added Risc-V register information file generation to the compiler Makefile 
* more stringent naming of register file information for Risc-V
 2022-05-31 22:38:30 +02:00
florian
ae457a18ad * unified Risc-V 32 and 64 register data file 2022-05-30 21:10:34 +02:00
florian
4556cb35d1 + completed Risc-V 64 pseudo instructions 
* typo fixed
 2022-05-28 21:22:11 +02:00
florian
6a00f9f403 * unified Risc-V 32 and 64 cpubase.pas 2022-05-28 21:15:53 +02:00
florian
09587d0c1b * standard Risc-V pseudo instructions for Risc-V 32 completed 2022-05-28 20:47:58 +02:00
florian
b29b81ae7b * pseudo instructions for flag handling 2022-05-28 20:25:28 +02:00
pierre
c2c7982a22 Fix check that third parameter of ADDI hp1 instruction is a constant 
git-svn-id: trunk@49467 -
 2021-06-02 19:58:38 +00:00
florian
9e2bcd940a + RiscV: initial OpAddi02Op implementation 
git-svn-id: trunk@49002 -
 2021-03-18 21:49:25 +00:00
florian
9ccdf2b3bf * RiscV: unified itcpugas.pas 
git-svn-id: trunk@48960 -
 2021-03-14 10:29:23 +00:00
pierre
9775a13e02 Rough fix for riscv32 failure 
git-svn-id: trunk@48959 -
 2021-03-14 09:10:29 +00:00
florian
e047e7db91 + RiscV: initial support of pic generation 
git-svn-id: trunk@48947 -
 2021-03-13 16:18:00 +00:00
florian
d1fb44044f * unified RiscV32 and RiscV64 GAS readers 
git-svn-id: trunk@48894 -
 2021-03-07 08:53:03 +00:00
florian
6f3fccddd1 * RiscV32: properly read references with record offsets and base register 
+ RiscV32: sanity check in assembler writer

git-svn-id: trunk@48892 -
 2021-03-06 22:19:00 +00:00
florian
c15bb07bf6 * do not generate mul instructions if the mul extension is not available 
git-svn-id: trunk@48883 -
 2021-03-06 14:23:54 +00:00
pierre
01a351f804 Fix for bug report 38549 about wrong code generation 
for mips/mipsel and riscv32/riscv64 CPUs for 
  set operators '<=' and '>='.
  New tests for this bug report.
  tw38549.pp, main source, also included 
  by tw38549a.pp, tw38549b.pp, tw38459c.pp and tw38459d.pp
  with explicit {$packset X}, with X=1,2,4, or 8 added.

git-svn-id: trunk@48874 -
 2021-03-03 22:15:20 +00:00
florian
5cd4e5a016 * pass lp64d to GNU AS for abi_riscv_hf to get the right ABI set 
git-svn-id: trunk@47585 -
 2020-11-25 20:20:08 +00:00
florian
637976e83f * patch by Marģers to unify internal error numbers, resolves #37888 
git-svn-id: trunk@47103 -
 2020-10-13 19:59:01 +00:00
pierre
d4c9e1f260 Replace outdated cgop2string function by tcgsize2str function from cgbase unit to fix EXTDEBUG cycle on powerpc64le-linux 
git-svn-id: trunk@46689 -
 2020-08-25 13:29:16 +00:00
nickysn
3d81dd0b00 * ReplaceForbiddenAsmSymbolChars renamed ApplyAsmSymbolRestrictions, because now it also applies the 
label length limit

git-svn-id: branches/z80@45085 -
 2020-04-26 10:42:07 +00:00
nickysn
a8fe46c0f5 + introduced labelmaxlen in tasminfo and added code in ReplaceForbiddenAsmSymbolChars that limits the 
output label to that length

git-svn-id: branches/z80@45066 -
 2020-04-25 12:59:25 +00:00
Jeppe Johansen
2678522db5 - RISC-V: Add controller types for common RV32 MCUs. 
- Adds initial controller units for these MCUs.

Code contributed by Michael Ring

git-svn-id: trunk@43935 -
 2020-01-13 22:54:26 +00:00
Jeppe Johansen
02c3f328a2 - RISC-V: Share optimizations between 32 and 64-bit. 
git-svn-id: trunk@43934 -
 2020-01-13 22:49:23 +00:00
svenbarth
114c27fb4e * increase support for multilib binutils for RISC V by passing the ABI to the assembler 
git-svn-id: trunk@43788 -
 2019-12-25 15:23:21 +00:00
pierre
4e4f55ac0e Comparison nodes are always in LOC_REGISTER, never in LOC_JUMP for riscv32 or riscv64 CPUs 
git-svn-id: trunk@43614 -
 2019-11-29 23:28:05 +00:00
pierre
92b0ea7d02 Add explicit smallint typecast to first marameter of SarSmallint call to avoid range check errors 
git-svn-id: trunk@43613 -
 2019-11-29 23:26:45 +00:00
pierre
8ea92a8280 Use correct macro to for 64-bit riscv CPU 
git-svn-id: trunk@43561 -
 2019-11-22 21:29:19 +00:00
florian
b3ed34592f + software handling of exceptions on arm 
* reworked software handling of exceptions so they can be check lazily

git-svn-id: trunk@42525 -
 2019-07-28 21:06:36 +00:00
Jonas Maebe
3fee990218 * on Mach-O, PECOFF and ELF platforms, write local symbols as hidden/ 
private_extern (or plain global in case of PECOFF, as the effect is
    the same there): visible across object files, but they become local
    when linked into a binary/library. This enables cross-unit inlining
    of functions accessig implementation-only symbols.

git-svn-id: trunk@42340 -
 2019-07-07 21:33:43 +00:00
Jeppe Johansen
a1a17447ff - Fix bug in 64bit softfloat double negation. 
- Clean up handling of CPU/FPU type handling in RISCV.
- Do more fixes to get RISCV32 working.
- Fix most soft multiplication handling for generic RISCV code. Still missing a few.
- Add RISCV embedded targets.

git-svn-id: trunk@42335 -
 2019-07-07 11:32:27 +00:00
Jonas Maebe
1b6425176b * synchronised with trunk till r42049 
git-svn-id: branches/debug_eh@42050 -
 2019-05-12 18:44:05 +00:00
Jonas Maebe
281b3ad276 * fix case completeness and unreachable code warnings in compiler that would 
be introduced by the next commit

git-svn-id: trunk@42046 -
 2019-05-12 14:29:03 +00:00
Jonas Maebe
a0f850d57f * synchronised with trunk till r41885 
git-svn-id: branches/debug_eh@41886 -
 2019-04-16 16:20:44 +00:00
Jeppe Johansen
2b78a8fd3d - Add support for .option directive in riscv assembler. 
- Use addiw when adjusting U32 to S32

git-svn-id: trunk@41870 -
 2019-04-14 20:51:29 +00:00
Jonas Maebe
a079e5fa80 * synchronised with trunk till r41449 
git-svn-id: branches/debug_eh@41450 -
 2019-02-24 20:01:53 +00:00
Jonas Maebe
07bd4ba517 * let all the case code generation work with tconstexprint instead of aint, 
so it also works for 32 bit targets and a high level code generator
    (where aint is still 32 bit, but 64 bit operations are not decomposed)

git-svn-id: trunk@41441 -
 2019-02-24 19:58:37 +00:00
Jonas Maebe
4cd6f59bc3 * changed create_hlcodegen into a procvar, so that we don't have to insert 
hlcgllvm in the uses clause of every unit that calls create_hlcodegen
   o prevents dependency cycles that can cause llvm codegen units to init
     before the cpu variants, which is bad since the llvm versions have to
     override the cpu variants in their init code (+ added checks in the
     init code that they are in fact initialised later)

git-svn-id: branches/debug_eh@40410 -
 2018-11-29 21:31:15 +00:00
pierre
11851d274c Fix riscv32 compilation error introduced in last commit 
git-svn-id: trunk@40323 -
 2018-11-16 10:24:27 +00:00
pierre
7c92412c74 Avoid overflow error in riscv code generator 
git-svn-id: trunk@40318 -
 2018-11-15 16:57:57 +00:00
Jonas Maebe
1a9eb77698 * fixed compilation with -O3 (one false positive, one real error) 
git-svn-id: trunk@40155 -
 2018-11-01 20:39:38 +00:00
pierre
aa89182bf5 Fix compilation with -dEXTDEBUG 
git-svn-id: trunk@39923 -
 2018-10-13 11:34:53 +00:00
Jeppe Johansen
d33b520690 Clean up peephole optimization code. 
Add hardfloat ABI option for RiscV. Still needs proper implementation though.
Add CG support for profiling.

git-svn-id: branches/laksen/riscv_new@39798 -
 2018-09-24 17:15:22 +00:00
Jeppe Johansen
576ef934bd Fix bug in lui+addi immediate load for spilling code. 
git-svn-id: branches/laksen/riscv_new@39764 -
 2018-09-16 20:51:15 +00:00