- Moved the part that emits the CMOV command outside of the if-else block, because it's the same in both branches and was just duplicated code.
- Moved a comment about powers of 2 to be right before the correct if-else block.
- Added a couple of comments to explain what the algorithm is doing to obtain the remainder.
- Added missing "writeln('ok');" (since 'tmoddiv3.pp' has it) and program header to 'tmoddiv4.pp'.
- Changed program name from "testfile2" to "tmoddiv3" in 'tmoddiv3.pp'.
git-svn-id: trunk@37939 -
inline assembly, and fixed check after r35959 (mantis #32318)
o can also subscript parameters passed by value on the stack
o can also subscript local variables, the parameters passed by reference
that are subsequently copied into a local
git-svn-id: trunk@37886 -
retfq x86 instructions. These are variants of the ret instruction with the
return offset size set explicitly, e.g. retfw is a 16-bit far ret (i.e. pops
a 16-bit offset and a 16-bit segment), retfd is a 32-bit far ret (pops a
32-bit offset, followed by a 16-bit segment), etc.
git-svn-id: trunk@37571 -
instructions got erroneously converted to 'jmp/call v', if 'v' is an external
far variable that points to certain things (like a local label, exported via
public)
git-svn-id: trunk@37538 -
warning (on the i8086 target) or an error (on i386 and x86_64) when this
instruction is used (because it only works on 8086 and 8088 CPUs)
git-svn-id: trunk@37514 -
default segment base for the ref, in case there's no segment override
* in the internal assembler, use get_default_segment_of_ref to strip redundant
prefixes, instead of always assuming all refs are DS-based
git-svn-id: trunk@37486 -
* taicpu.needaddrprefix now uses is_32_bit_ref on x86_64
* is_16/32/64_bit_ref made part of the aasmcpu unit interface, so they can be
used elsewhere (e.g. in the inline assembler readers)
git-svn-id: trunk@37469 -
specified to be (%esi) or (%edi), when using at&t syntax assembler (this is
not considered an error by intel syntax assemblers, so we're not adding a
warning there, for now)
git-svn-id: trunk@37458 -
* when generating x86 code for parameterized string instructions with the
internal object writer, don't rely on the destination operand being [(r/e)di]
when determining the segment prefix, because when using intel syntax, source
and destination can be anything (only the operand size, the address size and
the source segment is taken into account)
git-svn-id: trunk@37452 -
is_x86_parameterless_string_instruction_op and
is_x86_parameterized_string_instruction_op by removing 'instruction' from
their names
git-svn-id: trunk@37451 -
get_x86_string_op_size
* refactored the AT&T inline asm handling of x86 parameterized string ops, so it
uses the new helper functions
git-svn-id: trunk@37449 -
(movs, cmps, scas, lods, stos, ins, outs) in the inline asm of the i8086, i386
and x86_64 targets. Both intel and at&t syntax is supported.
* NEC V20/V30 instruction 'ins' (available only on the i8086 target, because it
is incompatible with 386+ instructions) renamed 'nec_ins', to avoid conflict
with the 186+ 'ins' instruction.
git-svn-id: trunk@37446 -
* changed most of the variables in the assembler readers used to store constants from aint to tcgint
as aint has only the size of the accumular while some CPUs (AVR) allow larger constants in instructions
+ allow access to absolute symbols with address type in inline assembler
* allow absolute addresses in avr inline assembler
+ tests
git-svn-id: trunk@37411 -
(16-bit and 32-bit), i386 (16-bit and 32-bit) and x86_64 (32-bit and 64-bit).
Known bug: 32-bit addresses with an offset have their offset truncated to its
low 16-bits on i8086
git-svn-id: trunk@37409 -
process_ea_ref_64_32, process_ea_ref_32 and process_ea_ref_16, indicating
the address size they support; this is done, so that in the future, we can
mix them all on the same x86 architecture and support multiple address sizes
git-svn-id: trunk@37407 -
o improves readibility of TX86AsmOptimizer.OptPass1MOV and fixes some spelling mistakes
+ Optimization MovAnd2Mov 2
+ extended Optimization MovTestJxx2TestMov and MovTestJxx2ovTestJxx to take care of and as well
+ Peephole Optimization: movq x,%reg -> movd x,%reg
git-svn-id: trunk@37377 -
* Disable asd_cpu for wasm (generates errors as it disabled the .xmm added at start)
- Remaining problem: 'DT inf' Error: not implemented ...
git-svn-id: trunk@37325 -
easily and so that all the values are now available to the compiler
(previously, there were several, which were mapped to the same value and thus
were only used to make x86ins.dat easier to read)
git-svn-id: trunk@37299 -
from cpubase unit to a method in the tcg class. The reason for doing that is
that this is now a standard part of the 16-bit and 8-bit code generators and
moving to the tcg class allows doing extra checks (not done yet, but for
example, in the future, we can keep track of whether there was an extra
register allocated with getintregister and halt with an internalerror in case
GetNextReg() is called for registers, which weren't allocated as a part of a
sequence, therefore catching a certain class of 8-bit and 16-bit code
generator bugs at compile time, instead of generating wrong code).
- removed GetLastReg() from avr's cpubase unit, because it isn't used for
anything. It might be added to the tcg class, in case it's ever needed, but
for now I've left it out.
* GetOffsetReg() and GetOffsetReg64() were also moved to the tcg unit.
git-svn-id: trunk@37180 -
(i386 and x86_64) code generator (same as the division by a positive power of
2, followed by a NEG instruction, to invert the sign of the result; previously
the code generator generated an IMUL instruction with a magic constant,
followed by shift; the new code sequence should be both shorter and faster)
git-svn-id: trunk@37003 -
with calls to cg.a_op_const_reg in the x86 div code generator, so that the
same code can be used in the future for i8086 as well (SHR and SAR by
constants other than 1 are 186+, so on 8086 they have to go through the CL
register, which is handled correctly in cg.a_op_const_reg)
git-svn-id: trunk@36815 -
the intel assembler reader: no longer parse them as register tokens,
but as local operands that are later converted into registers. This
ensures in particular that the type of the operand is set, which is
necessary in case this operand later subscripted (as in tasm10a)
git-svn-id: trunk@36288 -
determine whether it's in a register if it's a pure assembler routine
* you can't "index" implicit pointers either using their fields
git-svn-id: trunk@36287 -
register size for OP_SHR/OP_SHL/OP_SAR/OP_ROL/OP_ROR in tcgx86.a_op_reg_reg().
This is required for the in_[shr/shl/sar/rol/ror]_assign_x_y inline nodes.
git-svn-id: trunk@36251 -
* compinnr.inc include file converted to a unit
* inline number field size stored in ppu increased from byte to longint
* inlines in the parse tree (when written with the -vp option) now printed with
their enum name, instead of number
git-svn-id: trunk@36174 -
instead of SuperRegistersEqual in TX86AsmOptimizer.RegLoadedWithNewValue, so
it returns correct information for the 16-bit and 8-bit subregisters
(including AH,BH,CH and DH)
git-svn-id: trunk@36066 -
which takes into account how 16-bit and 8-bit subregisters work on the x86
(the new function is not used for now, but is probably going to replace
SuperRegistersEqual in a few specific places (in RegLoadedWithNewValue),
so that our register tracking becomes more accurate for 8-bit and 16-bit
subregisters)
git-svn-id: trunk@35990 -
directly in inline assembly: that's only possible if it's a register
parameter where the address of the record was passed (rather than the
record itself), or if a parameter has been explicitly typecasted in
Intel-style assembly using ".size"
git-svn-id: trunk@35959 -
this removes the limit of 3 Ch_XXX flags per instruction (thus allowing adding
more precise flags, e.g. for tracking only certain bits of the flags register,
etc.) and avoids the ugliness of having the Ch_None filler, which makes
x86ins.dat less readable.
git-svn-id: trunk@35850 -
* AAA and AAS also read flags (AF)
* CMC reads and writes flags (it inverts CF)
* CMPSx and SCASx write flags
* CMPSx, SCASx, LODSx, STOSx, MOVSx read the direction flag
* NOT doesn't affect flags
* REP isn't affected by and doesn't affect flags
* REPE/REPNE/REPZ/REPNZ/REPC/REPNC don't write flags, only read them
* ROL and ROR don't read flags
* SAL doesn't read flags
* SHLD and SHRD don't read flags
git-svn-id: trunk@35849 -
be used (TBD in a future commit) for optimizing x:=-x and x:=not x on CPUs
that support performing these operations directly in memory (such as x86)
git-svn-id: trunk@35749 -
* tasm2.pp already detected this bug if run with -al option. Added a copy of tasm2.pp and configured it with -al, so it is run daily on all suitable machines.
git-svn-id: trunk@35626 -
