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301 Commits

Author SHA1 Message Date
pierre
cc537a2e76 Try to avoid uncorrect optimization 
git-svn-id: trunk@29373 -
 2015-01-02 23:00:22 +00:00
sergei
b46ce6b70e * Fixed condition to output div/divu having R0 as first operand as non-macros. 
git-svn-id: trunk@29359 -
 2014-12-29 23:19:01 +00:00
sergei
57094d495b + MIPS: implement inline full 64-bit multiplication, for cases when overflow checking is off and CPU is set to mips32r2. 
git-svn-id: trunk@29354 -
 2014-12-28 22:03:15 +00:00
florian
5c67fcc43f + change always floating point divisions into multiplications if they are a power of two, 
this is an exact operation so it is always allowed
* change only divisions by normal numbers into multiplications

git-svn-id: trunk@29085 -
 2014-11-16 20:47:38 +00:00
sergei
a4053370fc * ELF linker: track relocation style (REL or RELA) of each input section and use it instead of global default on MIPS targets. This fixes internal linking of tests/test/units/system/tres*.pp. 
git-svn-id: trunk@29070 -
 2014-11-13 22:10:53 +00:00
Tomas Hajny
dc1446d32a * fixed misplaced constant definition 
git-svn-id: trunk@29053 -
 2014-11-10 13:51:50 +00:00
Tomas Hajny
3ee3542744 * boolean constant instead of IFDEFs for detection of microcontroller support 
git-svn-id: trunk@29052 -
 2014-11-10 12:34:59 +00:00
sergei
06ee500352 * MIPS: improved code generation in make_simple_ref 
* Clean up the peephole optimizer
+ More peephole optimizations.

git-svn-id: trunk@28892 -
 2014-10-21 21:05:46 +00:00
sergei
f85a8159ef * compiler/mips/cpuinfo.pas: removed "FPU_" prefixes from FPU names, not necessary because compiler inserts one itself. 
* rtl/embedded/system.pp: removed (commented out) FPU initialization from initialization of system unit, was dead code anyway because FPC_HAS_FEATURE_FPU is never defined and "feature FPU" does not exist.
* rtl/mips/*.inc: don't compile FPU instructions if compiling RTL with -CfNONE or -CfSOFT (however, handling these switches for MIPS targets in compiler needs further fixing).

git-svn-id: trunk@28670 -
 2014-09-15 18:24:23 +00:00
sergei
84245a6e0c * MIPS: doing progress with peephole optimizer. 
git-svn-id: trunk@28628 -
 2014-09-08 23:24:43 +00:00
sergei
3ede5ec99b * MIPS peephole: refactored/simplified and added (another) couple of optimizations. 
git-svn-id: trunk@28591 -
 2014-09-03 20:00:42 +00:00
sergei
ac64c4600f + MIPS: make use of instructions MUL,SEB and SEH that are available in modern cores. 
git-svn-id: trunk@28590 -
 2014-09-03 19:59:00 +00:00
sergei
4e2fb9d28b * MIPS: fixed O_MOVE_SOURCE and O_MOVE_DEST constants (they were swapped, amazing that it ever worked with such a mistake). 
+ Spilling for SEB and SEH
* Another attempt to get spilling of 3-operand form DIV/DIVU be done correctly.

git-svn-id: trunk@28588 -
 2014-09-03 19:57:46 +00:00
sergei
406a678223 * MIPS: MOVE instruction cannot be changed into conditional move (MOVZ/MOVN) if it overwrites register used as condition. 
git-svn-id: trunk@28587 -
 2014-09-03 11:59:16 +00:00
sergei
02f39c667a * MIPS: added a couple of important capabilities and made them available for big-endian targets as well. 
git-svn-id: trunk@28581 -
 2014-09-02 12:51:48 +00:00
sergei
768e090006 - MIPS: don't create reg.allocator for MM registers. 
git-svn-id: trunk@28579 -
 2014-09-01 21:55:03 +00:00
sergei
1e11e34f42 + MIPS: implemented more peephole optimizations. 
git-svn-id: trunk@28536 -
 2014-08-29 18:20:49 +00:00
sergei
d9a7d28838 + MIPS: support floating point conditions in its emulated flags, on MIPS4+ convert such flags to registers using conditional move instructions (i.e. without branching). For older cores generated code remains the same. 
git-svn-id: trunk@28535 -
 2014-08-29 18:18:17 +00:00
sergei
3b06465322 + MIPS: support replacement spilling for mov.s, mov.d and (partially) mtc1 instructions. 
git-svn-id: trunk@28530 -
 2014-08-27 21:26:38 +00:00
sergei
5655baa23a * MIPS: optimized conversion of unsigned 32-bit integers to float, now uses one integer register instead of two and does not generate redundant move. 
git-svn-id: trunk@28529 -
 2014-08-27 21:23:47 +00:00
sergei
f0496001fb - MIPS: removed allocation of stack/frame pointer registers in prologue, hacks like this are no longer needed since r27104. 
git-svn-id: trunk@28505 -
 2014-08-21 19:36:00 +00:00
Károly Balogh
d22dc68fda * fixed DFA warnings for MIPS and AVR 
git-svn-id: trunk@28502 -
 2014-08-20 15:05:43 +00:00
sergei
482e61dafa * MIPS, TCpuAsmOptimizer.GetNextInstructionUsingReg: test that returned item is actually an instruction, because GetNextInstruction can sometimes stop on labels. 
+ Try to eliminate register move after instructions that load from memory.

git-svn-id: trunk@28380 -
 2014-08-10 21:31:13 +00:00
sergei
f1d1fd4f24 * Inserted explicit typecasts in order to prevent range check errors at some places where signed and unsigned types are assigned to each other (mostly MIPS-specific, but one was necessary in generic code). 
git-svn-id: trunk@28379 -
 2014-08-10 21:26:14 +00:00
sergei
e4fea2ebc8 * Dummy implementations of a_bit_scan_reg_reg and g_stackpointer_alloc in tcg, removes the need to override these methods in every descendant code generator solely to avoid "constructing a class with abstract method" warning. 
git-svn-id: trunk@28175 -
 2014-07-06 11:34:04 +00:00
sergei
e367ccc0ee * MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names. 
* Change register type of second operand in CTC1 and CFC1 instructions to R_SPECIALREGISTER, so it is not output using a symbolic name. Mantis #26380.

git-svn-id: trunk@28034 -
 2014-06-22 22:01:44 +00:00
sergei
c2a29a0dbb + MIPS: implemented peephole optimization which changes appropriate patterns into conditional moves, which are available on MIPS4 and higher. 
git-svn-id: trunk@28008 -
 2014-06-20 05:57:39 +00:00
sergei
4e7c908b0d + MIPS: added movn and movz instructions. 
git-svn-id: trunk@28007 -
 2014-06-19 22:44:17 +00:00
sergei
25037f5318 - MIPS: completely removed trgcpu.add_constraints method. 
While it can be correct from some point of view, it does not prevent aliasing a single-precision register into upper half of double-precision one. This is currently handled by making only even floating-point registers available to RA. At the same time, it somehow (possibly due to another bug in RA) generates a lot of unnecessary moves, as if physical double-precision registers conflict with each other. Anyway, removing it considerably improves the code without regressions in the test suite.

git-svn-id: trunk@27999 -
 2014-06-19 03:59:24 +00:00
sergei
c260879439 * MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7). 
* cpubase.pas, std_regname: changed logic to lookup known names for special registers before resorting to default name, so that $fcc0..$fcc7 can be used as operands.

git-svn-id: trunk@27992 -
 2014-06-17 23:15:34 +00:00
sergei
c77225d2c4 + MIPS: added some instructions. 
git-svn-id: trunk@27991 -
 2014-06-17 22:52:35 +00:00
sergei
a8e30043db + MIPS: more peephole optimizations (basically updated to the state of SPARC peephole). 
git-svn-id: trunk@27990 -
 2014-06-17 22:50:29 +00:00
sergei
244f65525b * MIPS: dropped gas_std_regname, its functionality merged into std_regname. This fixes register names in non-instructions (reg. allocation information, variable locations, etc.) and makes assembler listings more readable. 
git-svn-id: trunk@27986 -
 2014-06-16 22:52:56 +00:00
sergei
cd27d64cd5 + Support (as target-independent as possible) optimization of division by constants: 
The code generator gets two new methods, a_mul_reg_reg_pair and g_div_const_reg_reg. The first one is basically 32x32 to 64 bits multiplication (or any other size, with result having twice the size of arguments), which must be implemented for every target. The second one actually does the job, its default implementation taken from powerpc64 and is sufficiently good for all three-address targets.

+ Enabled optimized division for MIPS target, target-specific changes are under 30 lines.

git-svn-id: trunk@27904 -
 2014-06-08 22:50:24 +00:00
sergei
c76dedfd31 * MIPS: re-enable peephole optimizations which got disabled by r27106 and were not restored in r27147. Unfortunately such things are hard to detect reliably in automated way. 
git-svn-id: trunk@27852 -
 2014-06-04 22:34:46 +00:00
sergei
4202343033 * MIPS: emit ".set nomips16" and ".set noreorder" directives for procedures declared as "assembler nostackframe", as it is done for regular procedures. Handwritten assembler routines typically utilize delay slots, and it is desirable that assembler does not mess it up. 
git-svn-id: trunk@27847 -
 2014-06-04 00:26:44 +00:00
svenbarth
02495c17bd Fix a typo. The CPU specific version of "ttypesym" should be called "tcputypesym" and not "tcpuypesym". 
git-svn-id: trunk@27531 -
 2014-04-11 14:30:59 +00:00
sergei
96dd464bf2 * Moved fixup_jmps to target-specific classes for powerpc,powerpc64 and MIPS, cleaned out remaining $ifdef's. A slight functionality change is that fixup_jmps is now called before adding the procedure end symbol, not after, but that should not matter. 
git-svn-id: trunk@27450 -
 2014-04-02 14:17:23 +00:00
Jonas Maebe
d452686c39 * moved pbestrealtype from symdef to symcpu 
git-svn-id: trunk@27441 -
 2014-04-01 21:41:37 +00:00
Jonas Maebe
f101118cd6 * moved MIPS-specific tprocdef.total_local_size field to cpu-specific 
descendant

git-svn-id: trunk@27436 -
 2014-04-01 21:41:21 +00:00
Jonas Maebe
dae5d1ff62 + added class reference types of the architecture-specific t*def/t*sym 
classes

git-svn-id: trunk@27396 -
 2014-03-30 21:04:32 +00:00
Jonas Maebe
b57c95043f + support overriding tdef/tsym methods with target-specific functionality: 
o made all (non-abstract) tdef and tsym constructors virtual
   o added c*def/c*sym classref types for every (non-abstract) t*def/t*sym
     class
   o added cpusym unit for every architecture that derives a tcpu*def/tcpu*sym
     class from the base classes, and initialises the c*def/c*sym classes with
     them. This is done so that the llvm target will be able to derive from
     the tcpu*def/sym classes without umpteen ifdefs, and it also means that
     the WPO can devirtualise everything because the c* variables are only
     initialised with one class type
   o replaced all t*def/t*sym constructor calls with c*def/c*sym constructor
     calls

git-svn-id: trunk@27361 -
 2014-03-29 22:31:55 +00:00
florian
b2b26f84cf * partially merged the mips-embedded branch of Michael Ring: 
- startup code/controller units are not merged yet
  - assembler call does not pass the needed CPU type yet

git-svn-id: trunk@27188 -
 2014-03-19 21:25:38 +00:00
sergei
e163a2c813 * MIPS and SPARC: determine whether case expression is in range using a single unsigned comparison (like it is done on other targets). 
git-svn-id: trunk@27088 -
 2014-03-10 23:02:05 +00:00
Jonas Maebe
4065483a50 * completed thlcgobj.location_force_fpureg(), use it everywhere and removed 
ncgutil/thlcg2ll.location_force_fpureg()

git-svn-id: trunk@27071 -
 2014-03-10 09:01:05 +00:00
sergei
87684e1cf1 * MIPS: clean up 
git-svn-id: trunk@26946 -
 2014-03-04 08:42:45 +00:00
sergei
46f8e78d1f + Support GOT/gp-relative constants in GAS and internal assemblers, MIPS and i386. 
* Change MIPS jump tables in PIC mode to use gp-relative constants, making them ABI-compliant and not requiring dynamic relocations.

git-svn-id: trunk@26886 -
 2014-02-26 14:54:47 +00:00
sergei
ed1555b918 * Moved generation of .ent/.end directives out of generic code generator. 
* Generation of .ent/.end directives for Alpha is dropped, but that target has more important issues to solve.

git-svn-id: trunk@26757 -
 2014-02-12 17:30:48 +00:00
sergei
d7c7ee2c2a * MIPS: fixed 8/16 bit arithmetic shifting to be done without using an additional register. 
git-svn-id: trunk@26736 -
 2014-02-08 21:13:58 +00:00
sergei
d29300df13 * tMIPSELnotnode.second_boolean: reuse common handle_locjump method. 
git-svn-id: trunk@26735 -
 2014-02-08 21:10:01 +00:00