paweld/fpc
1
0
Fork 0
mirror of https://gitlab.com/freepascal.org/fpc/source.git synced 2025-10-18 10:11:37 +02:00
Code Issues Packages Projects Releases Wiki Activity
51,705 Commits 102 Branches 76 Tags 325 MiB
aefa317474
Commit Graph

1297 Commits

Author SHA1 Message Date
nickysn
aefa317474 + fast and branchless implementation of abs(int64) for i386 
git-svn-id: trunk@37169 -
 2017-09-10 17:25:47 +00:00
florian
22956c4393 + TX86AsmOptimizer.OptPass1OP 
git-svn-id: trunk@36365 -
 2017-05-28 13:49:43 +00:00
florian
912e6d129a * fix modification flags for *ROUND* 
git-svn-id: trunk@36280 -
 2017-05-21 11:12:57 +00:00
florian
ddfaf59626 * fix compilation with -Cr 
git-svn-id: trunk@36276 -
 2017-05-21 08:34:42 +00:00
florian
0f16f6d94d + OptPass1MOVXX 
git-svn-id: trunk@36209 -
 2017-05-14 20:59:10 +00:00
florian
535c990233 + OptPass1MOVAP 
git-svn-id: trunk@36203 -
 2017-05-13 21:48:44 +00:00
florian
f4a29bb75d * moved InstructionLoadsFromReg and RegReadByInstruction from TCpuAsmOptimizer (i386) to TX86AsmOptimizer 
git-svn-id: trunk@36200 -
 2017-05-13 09:58:25 +00:00
nickysn
efc5e339d0 * use an enum instead of integer constants to represent inline numbers 
* compinnr.inc include file converted to a unit
* inline number field size stored in ppu increased from byte to longint
* inlines in the parse tree (when written with the -vp option) now printed with
  their enum name, instead of number

git-svn-id: trunk@36174 -
 2017-05-10 14:41:43 +00:00
florian
b1dff29cbf * removed unused units 
git-svn-id: trunk@36165 -
 2017-05-09 19:53:14 +00:00
florian
52d3756c26 * factored out OptPass1Movx and merged i386 and x86-64 version 
git-svn-id: trunk@36159 -
 2017-05-08 20:44:27 +00:00
florian
06c4c651fd * factored out PrePeepholeOptSxx 
+ x86-64 uses PrePeepholeOptSxx now as well

git-svn-id: trunk@36158 -
 2017-05-08 20:44:24 +00:00
florian
dd69ab5488 * cleanup after all old code from PeepHoleOptPass2 of i386 was moved to the common x86 optimizer class 
git-svn-id: trunk@36147 -
 2017-05-07 16:18:37 +00:00
florian
cd134ea5bb + DebugMsg 
git-svn-id: trunk@36146 -
 2017-05-07 16:18:35 +00:00
florian
7afe762d22 * factored out OptPass2Jcc assembler optimization 
* OptPass2Jcc now used by x86-64 as well
* remove orphaned alignments if the label is not used anymore after cmov is used

git-svn-id: trunk@36143 -
 2017-05-07 12:45:48 +00:00
florian
e3f0b338d4 * SkipLabels moved to aoptutils 
* factored out OptPass2Jmp assembler optimization
* OptPass2Jmp now used by x86-64 as well

git-svn-id: trunk@36141 -
 2017-05-06 21:07:02 +00:00
nickysn
af48d176ec + precise flag information for the ucomiss,ucomisd,vucomiss and vucomisd x86 instructions 
git-svn-id: trunk@36115 -
 2017-05-05 13:41:43 +00:00
nickysn
0cd70844f1 + take into account the fact that lea doesn't read the segment register of its 
reference in i386's TCpuAsmOptimizer.RegReadByInstruction

git-svn-id: trunk@36080 -
 2017-05-04 14:13:53 +00:00
nickysn
d5d53e7017 * fixed operand order in the check for sse movsd in i386's 
TCpuAsmOptimizer.RegReadByInstruction

git-svn-id: trunk@36003 -
 2017-04-28 14:56:54 +00:00
nickysn
ff1ee6836d + fix RegReadByInstruction for the x86 MOVSD instruction 
git-svn-id: trunk@35968 -
 2017-04-27 14:42:08 +00:00
nickysn
b741e38f98 + precise handling for x86 conditions and their flag bits in i386's 
TCpuAsmOptimizer.RegReadByInstruction

git-svn-id: trunk@35965 -
 2017-04-27 12:07:48 +00:00
nickysn
0f010430cc + better precision in determining the registers, read by mul/imul/div/idiv in 
i386's TCpuAsmOptimizer.RegReadByInstruction:
  * mul doesn't read edx (unless included in operand)
  * 8-bit mul and imul don't read ah (unless included in operand)
  * 8-bit div and idiv don't read edx (unless included in operand)

git-svn-id: trunk@35958 -
 2017-04-26 16:17:31 +00:00
nickysn
916c09af55 + also check the register type when checking for specific integer registers in 
i386's TCpuAsmOptimizer.RegReadByInstruction. Previously, the lack of this
  check could generate false reads on some other register types (e.g. mmx/xmm/
  flags, etc.), and this could worsen optimizations.

git-svn-id: trunk@35957 -
 2017-04-26 15:25:38 +00:00
nickysn
618b6292ee + support testing for individual bits from the x86 flags register in i386's 
TCpuAsmOptimizer.RegReadByInstruction()

git-svn-id: trunk@35956 -
 2017-04-26 14:38:36 +00:00
nickysn
c8487c4150 + added individual bits of the x86 flags register as subregisters 
git-svn-id: trunk@35955 -
 2017-04-26 13:52:52 +00:00
nickysn
5f66f5cebb + distinguish between x86 flags subregisters: flags, eflags and rflags 
git-svn-id: trunk@35953 -
 2017-04-25 16:10:43 +00:00
nickysn
0c244046a9 * proper register change info for the movs,cmps and scas x86 string instructions 
(movsd still todo, because of the overlap with the sse2 instruction)

git-svn-id: trunk@35929 -
 2017-04-23 21:30:25 +00:00
nickysn
1d34e96064 + added x86 instruction flag Ch_RFLAGScc, indicating instructions that read 
specific bits from the flags register, according to their condition (used by
  Jcc/SETcc/CMOVcc)

git-svn-id: trunk@35907 -
 2017-04-22 22:07:05 +00:00
nickysn
1146b7c12c + added detailed information for individual flag bits use for most x86 
instructions. Not used by the compiler yet, but may allow more
  optimizations in the future.

git-svn-id: trunk@35882 -
 2017-04-21 23:03:33 +00:00
nickysn
869f395a31 + added knowledge to the compiler for the x86 instructions, that don't read 
their input registers, in case both parameters are the same register (e.g.
  xor eax, eax; sub eax, eax; etc.)

git-svn-id: trunk@35861 -
 2017-04-20 15:11:56 +00:00
nickysn
af235cae86 * use TEST CL,32 instead of TEST ECX,32 in the beginning of a 64-bit shl/shr 
sequence on i386

git-svn-id: trunk@35856 -
 2017-04-19 21:30:31 +00:00
nickysn
12a1ad66b2 + added the Ch_RDirFlag change attribute to the STOSx instructions (previously 
was missing, due to the 3 attributes per instruction limit)

git-svn-id: trunk@35855 -
 2017-04-19 20:23:24 +00:00
nickysn
9303a8f61a * changed the x86 TInsProp.Ch structure from a 3-element array to a pascal set; 
this removes the limit of 3 Ch_XXX flags per instruction (thus allowing adding
  more precise flags, e.g. for tracking only certain bits of the flags register,
  etc.) and avoids the ugliness of having the Ch_None filler, which makes
  x86ins.dat less readable.

git-svn-id: trunk@35850 -
 2017-04-19 16:48:35 +00:00
nickysn
189e49998c * fixes to the x86 instruction flags tracking attributes: 
* AAA and AAS also read flags (AF)
  * CMC reads and writes flags (it inverts CF)
  * CMPSx and SCASx write flags
  * CMPSx, SCASx, LODSx, STOSx, MOVSx read the direction flag
  * NOT doesn't affect flags
  * REP isn't affected by and doesn't affect flags
  * REPE/REPNE/REPZ/REPNZ/REPC/REPNC don't write flags, only read them
  * ROL and ROR don't read flags
  * SAL doesn't read flags
  * SHLD and SHRD don't read flags

git-svn-id: trunk@35849 -
 2017-04-19 15:42:50 +00:00
nickysn
e708a76f70 * some i386 optimizations for 64-bit SHL/SHR/SAR in tcg64f386.a_op64_const_reg: 
* only use SHx/RCx when optimizing for size
  * use ADD reglo,reglo + ADC reghi,reghi for SHL by 1 on i386 and i486

git-svn-id: trunk@35841 -
 2017-04-18 21:30:31 +00:00
nickysn
0264c4cace + implemented OP_SHR/OP_SHL/OP_SAR correctly in tcg64f386.a_op64_const_ref for 
const values larger than 31

git-svn-id: trunk@35838 -
 2017-04-18 16:02:48 +00:00
nickysn
d7b8d8dd54 * don't emit the "SUB ECX,32" instruction on i386, when doing a 64-bit shift by 
reg, with a value >=32. The instruction is redundant, because the SHL/SHR
  instructions already AND mask the shift count by 31.

git-svn-id: trunk@35836 -
 2017-04-18 15:09:20 +00:00
nickysn
03dfa07ebc + implemented OP_SHR/OP_SHL/OP_SAR in i386's tcg64f386.a_op64_reg_ref 
git-svn-id: trunk@35834 -
 2017-04-18 14:34:20 +00:00
nickysn
10d7603dce + implemented OP_SHR/OP_SHL/OP_SAR support in tcg64f386.a_op64_reg_reg 
git-svn-id: trunk@35831 -
 2017-04-18 12:24:46 +00:00
nickysn
7e8c89435f * avoid the AND instruction in the i386 shr64/shl64 code, by using TEST+JZ, 
instead of CMP+JL

git-svn-id: trunk@35830 -
 2017-04-18 11:36:48 +00:00
nickysn
a1ad705646 + allocate and free flags before and after the shl+rcl/shr+rcr/sar+rcr sequences 
git-svn-id: trunk@35786 -
 2017-04-13 11:58:51 +00:00
nickysn
cddb48bad4 + i386 implementation of a_op64_const_reg for OP_SHR,OP_SHL and OP_SAR; needed 
by the in_shl/shr/sar_assign_x_y inline nodes

git-svn-id: trunk@35785 -
 2017-04-13 11:54:19 +00:00
nickysn
6a710964f2 + i386 implementation of a_op64_const_ref for OP_SHR,OP_SHL and OP_SAR; needed 
by the in_shl/shr/sar_assign_x_y inline nodes

git-svn-id: trunk@35784 -
 2017-04-13 10:38:33 +00:00
nickysn
256dc546ac + implemented the in_neg_assign_x and in_not_assign_x inline nodes, which will 
be used (TBD in a future commit) for optimizing x:=-x and x:=not x on CPUs
  that support performing these operations directly in memory (such as x86)

git-svn-id: trunk@35749 -
 2017-04-07 16:02:40 +00:00
nickysn
6580dfee39 * generate better i386 code for 64-bit shl/shr, by masking the shift count by 
63, instead of comparing it to 64 and branching. Note that, although this
  changes the behaviour of 64-bit shifts by values larger than 64 (when stored
  in a variable), it actually makes them consistent with both the code,
  generated on x86_64, as well as with 64-bit shift by constant on i386 itself.

git-svn-id: trunk@35727 -
 2017-04-04 16:28:54 +00:00
nickysn
5cb724edd9 + added optimized implementation of a_op64_reg_ref for i386 as well; improves 
generated code for inc(int64_var,int64_var) and dec(int64_var,int64_var)

git-svn-id: trunk@35660 -
 2017-03-25 21:40:20 +00:00
Jonas Maebe
4c68ea1000 * use pocalls_cdecl and cstylearrayofconst more consistently instead of 
ad hoc set constants containing varying number cdecl-like calling
    conventions
   o added pocall_sysv_abi_cdecl and pocall_ms_abi_cdecl to cstylearrayofconst
   o also allow C-style blocks with mwpascal instead of cdecl (mwpascal = cdecl
     with "const" = "constref" for record parameters)
   o did not touch cases related to name mangling and import/export names,
     because those are a real mess and easily break things left and right :/

git-svn-id: trunk@35479 -
 2017-02-25 11:46:35 +00:00
florian
f68558b88c * factored out TX86AsmOptimizer.OptPass2Imul 
git-svn-id: trunk@35252 -
 2017-01-06 22:25:24 +00:00
Jonas Maebe
880d438704 * renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can 
inherit from it for LLVM without a thousand ifdefs

git-svn-id: trunk@35141 -
 2016-12-16 22:41:21 +00:00
Károly Balogh
0cb555c07c syscalls: move the reference implementation of parseparaloc to paramgr. removes two identical copies from CPU specific code and enables basereg convention for AROS/x86_64. also, other minor fixes and cleanups in related code. 
git-svn-id: trunk@35047 -
 2016-12-03 19:00:41 +00:00
Károly Balogh
f5f895e2a3 syscalls: unify call reference creation across 4 different CPU archs. less copypasted code, brings x86_64 AROS support up to speed 
git-svn-id: trunk@35034 -
 2016-12-02 09:29:09 +00:00