The code generator gets two new methods, a_mul_reg_reg_pair and g_div_const_reg_reg. The first one is basically 32x32 to 64 bits multiplication (or any other size, with result having twice the size of arguments), which must be implemented for every target. The second one actually does the job, its default implementation taken from powerpc64 and is sufficiently good for all three-address targets.
+ Enabled optimized division for MIPS target, target-specific changes are under 30 lines.
git-svn-id: trunk@27904 -
o made all (non-abstract) tdef and tsym constructors virtual
o added c*def/c*sym classref types for every (non-abstract) t*def/t*sym
class
o added cpusym unit for every architecture that derives a tcpu*def/tcpu*sym
class from the base classes, and initialises the c*def/c*sym classes with
them. This is done so that the llvm target will be able to derive from
the tcpu*def/sym classes without umpteen ifdefs, and it also means that
the WPO can devirtualise everything because the c* variables are only
initialised with one class type
o replaced all t*def/t*sym constructor calls with c*def/c*sym constructor
calls
git-svn-id: trunk@27361 -
required for the LLVM support (LLVM parameter support is not yet
included)
* always return the function return loc from a_call*, again as required
for the LLVM support
git-svn-id: branches/hlcgllvm@26992 -
* Change MIPS jump tables in PIC mode to use gp-relative constants, making them ABI-compliant and not requiring dynamic relocations.
git-svn-id: trunk@26886 -
do_spill_replace routines, will be necessary by llvm register
allocator to determine the tdef corresponding to that register
* replaced uses of taicpu with tai_cpu_abstract_sym in the register
allocator so that it can work both with taicpu and taillvm instructions
git-svn-id: branches/hlcgllvm@26043 -
cgobj.pas, tcg:
* g_save_registers: add the amount of used address registers to size as well
* g_save_registers: save all used address registers
* g_restore_registers: restore all stored address registers
m68k/cpubase.pas:
* rename saved_standard_address_registers to saved_address_registers
all other platform's cpubase.{inc,pas} (except alpha, ia64 and vis which are not up to date):
* add a saved_address_registers variable with one entry of RS_INVALID
At least a "make fullcycle" did complete.
git-svn-id: trunk@25664 -
* Deallocate GP save temp in epilogue to avoid warnings when compiled with -dEXTDEBUG
* g_concatcopy: don't check alignment, this allows single byte or word locations to be copied with 2 instructions. Larger unaligned references are supposed to be handled in g_concatcopy_unaligned instead.
git-svn-id: trunk@25147 -
* Use fpc_[int64|qword]_to_double instead of [int64|qword]_to_float64, makes RTL no longer dependent on softfloat code.
* Move 32-bit values from integer registers to FPU registers without using memory.
* Fixed branching, was still using a macro and delay slot was missing.
git-svn-id: trunk@25071 -
The difference in branch instruction formats is isolated in function JumpTargetOp, it is a plain function rather than a virtual method, so it can be easily inlined and, after inlining, produces the same code for non-MIPS targets as it was before change.
git-svn-id: trunk@25033 -
* Moved jump tables into data segment. For disassembly-based stack unwinding to work properly, MIPS ABI expects text segment to contain instructions only.
git-svn-id: trunk@24904 -
+ Implemented subset of "spill replace" functionality, replacing moves from/to spilled registers with loads/stores to spill locations. This helps to reduce amount of instructions.
git-svn-id: trunk@24900 -
* Output registers of type R_SPECIALREGISTER as numbers.
+ For MTC0/MFC0 instructions, set type of first operand to R_SPECIALREGISTER, since it designates a coprocessor register.
git-svn-id: trunk@24799 -
contains the tcgsize of the entire parameter rather than only of
what is left (-> calculate it from the remaining parameter length)
git-svn-id: trunk@24776 -
- removed mips_cpu variable and cpu_mips_default CPU type.
* globals.pas: default CPU type changed to MIPS2, this is what was passed to assembler before.
git-svn-id: trunk@24643 -
- references cannot be in brackets
- registers are only prefixed by dollar, never by percent
- syntax x@LO is not supported, must be %lo(x).
git-svn-id: trunk@24633 -
* reworked condition codes, changed BC1T and BC1F from separate instructions to condition jumps.
- removed A_P_SW, A_P_LW and A_SPARC8UNIMP
+ support '.set at' and '.set noat' directives
+ prepare to support bgtz,bgez,bltz,blez instructions.
git-svn-id: trunk@24631 -
+ Implemented overflow checking for unsigned 32-bit addition and subtraction.
* Use optimize_op_const instead of custom optimizations.
* Change AND/OR/XOR into ANDI/ORI/XORI if they use immediate operands, and use correct range for these immediate operands, must be 0..65535 unlike -32768..32767 for arithmetic operations.
* Don't treat AND/OR/XOR as macros, no longer necessary.
* Don't treat BEQ/BNE as macros either.
git-svn-id: trunk@24445 -
* TCGMIPS.a_load_reg_reg: generate CPU instructions instead of macros
* TCGMIPS.a_cmp_const_reg_label: load constant using a_load_const_reg instead of LI macro (it may also end up with LI, but tries to optimize when possible).
- removed unused variables.
git-svn-id: trunk@24418 -
* shorter by 280 lines
* generates actual instructions instead of macros
* uses immediate operands for constants when possible
* 64-bit and float comparisons use LOC_JUMP as location
git-svn-id: trunk@24236 -
- Removed TMIPSProcInfo.needs_frame_pointer, it duplicates pi_needs_stackframe flag.
- Don't save RA for leaf procedures.
* GP is caller-saved register, it does not need saving/restoring as nonvolatile registers. Handle its restore position as a "normal" temp, whose offset is known before secondpass. This allows to handle PIC calls without involving GAS macro processing.
git-svn-id: trunk@23885 -
+ Favor 'weak' parameter in a_call_name of both thlcgmips and TCGMIPS.
* make_simple_ref and a_loadaddr_ref_reg: require input references to be 'raw' (no refaddr=addr_pic, etc) and do not use GP as base/index. If it's not true, raise an internal error. When addr_pic_call16 or so needs to be generated, it must be done without calling the mentioned methods.
* thlcgmips.a_call_name: generate PIC sequence for procedures declared as 'external', instead of 'cdecl', this is more correct because ABI has only one calling convention.
- make_simple_ref_fpu removed, there's no reason to handle references to floating-point data in different way.
- a_loadaddr_ref_cgpara override also removed, generic method does the job just well.
- thlcgmips.a_call_ref and a_call_reg overrides removed because indirect calls are now always done using $t9.
git-svn-id: trunk@23698 -
* Abort if attempting to emit a call without pi_do_call flag set, because the outgoing parameter area determines layout of temps and therefore cannot be created/changed during pass 2.
* Bypass g_concatcopy_move if procedure is a leaf one, due to the restriction mentioned above.
git-svn-id: trunk@23644 -
