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71,824 Commits 100 Branches 75 Tags 335 MiB
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98 Commits

Author SHA1 Message Date
florian
f65994ddcb + RiscV: flags for crypotography extensions 2025-03-26 22:44:26 +01:00
florian
c7290bfb78 * enclose {$define DEBUG_AOPTCPU} in {$ifdef EXTDEBUG} 2025-03-10 22:50:49 +01:00
florian
831a46eb2f + more sext.b usage 2025-02-25 22:50:14 +01:00
florian
e219b24aec * RiscV64: make use of sext.h instruction 2025-02-23 23:11:01 +01:00
florian
8e45bb133d + RV64GCB CPU type 2025-02-20 22:41:35 +01:00
florian
d842d822ff * RiscV64: make use of zext.w instruction if available 2025-02-19 22:44:03 +01:00
florian
e17c575123 * properly write RV32E/RV64E architecture tags 2025-01-28 22:38:59 +01:00
florian
95c2a5a2d7 + RiscV: support ZMMUL extension 2025-01-26 14:43:57 +01:00
florian
cfc5f17b0d + CPURV_HAS_ZICOND 2025-01-20 22:52:23 +01:00
florian
5bb4049737 * remove accidently committed debug statement 2025-01-12 11:32:34 +01:00
florian
971d97c179 + RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0 2025-01-11 21:03:54 +01:00
florian
c3110dfaa9 + RiscV: make use of the fneg.* instruction 2025-01-09 22:25:26 +01:00
florian
b7608b045b * RiscV: push_addr_param unified 2024-12-26 16:49:43 +01:00
florian
9ba3b12eaa * RiscV: unify push_addr_param 2024-12-25 23:33:11 +01:00
florian
57da25581e + write .option pic directive if needed 2024-12-25 18:35:46 +01:00
florian
8d0bdf2f16 + RiscV: vector registers 2024-12-25 10:34:46 +01:00
florian
49aa141703 * major parts of the RiscV paramgr unified, improves code generation and less failures in RiscV32 regression tests 2024-12-22 22:37:16 +01:00
florian
4bc9f64b70 * continued unification of RiscV paramgr 2024-12-19 22:55:36 +01:00
florian
d33e7920a2 * more RiscV paramgr unification 2024-12-16 22:50:46 +01:00
florian
98b1aee2a5 * more RiscV paramgr unification 2024-12-15 23:01:55 +01:00
florian
f32eaa1564 * skeleton to unify the RiscV paramgr 
* first routines unified
 2024-12-15 15:29:05 +01:00
florian
74bad92e4d * formatting 2024-12-14 19:19:05 +01:00
florian
0b49fba637 + more RiscV extensions 
* make use of F and D extension flags
 2024-11-17 15:05:35 +01:00
florian
1d629270ca * RiscV64: fix abs(<longint>) 2024-10-14 21:10:10 +02:00
florian
fdae200281 * RiscV64: don't use addiw for OS_32 to OS_32 type conversions obviously 2024-09-26 21:48:53 +02:00
florian
d247c30965 * RiscV64: better code generation to clear upper 32 bit of a register 2024-09-23 22:28:09 +02:00
florian
159d97e864 * Risc-V: make use of sext.h instruction if available 2024-08-15 21:53:04 +02:00
florian
a53eb8b230 + Risc-V: make use of zext.h if available 2024-08-14 22:37:26 +02:00
florian
0366df9fbd + Zb* cpu capabilities 2024-08-11 22:47:29 +02:00
florian
1ecc880fc8 + cpu type RV64GC 2024-08-07 22:53:10 +02:00
florian
e6ba09aedd + Risc-V 64: tcpuparamanager.get_saved_registers_int and tcpuparamanager.get_saved_registers_fpu 2024-08-06 22:56:35 +02:00
florian
39f7172ee8 * do no generated debug comment in assembler output of RiscV if not requested 2024-05-25 20:16:42 +02:00
florian
0a88683310 + do do_consttovar on RiscV 2024-05-25 20:09:02 +02:00
florian
f49da05633 * unified g_concatcopy_move 2024-05-15 22:52:24 +02:00
florian
52147baa04 * correct tripletcpustr, resolves #40301 2023-05-31 20:26:50 +02:00
florian
19ad26afd8 * Riscv32 and Riscv64 on linux: enable safecall support 2022-07-22 22:56:21 +02:00
Jeppe
f5cf8956c5 riscv: Merge stack code, fix interrupted code 
- Stack pointer is kept below register save area. This ensures that
registers are not overwritten by interrupt handlers.
- RV32 and 64 code is merged to base class.
 2022-07-02 15:07:42 +02:00
florian
eaeb8b70ff + added Risc-V register information file generation to the compiler Makefile 
* more stringent naming of register file information for Risc-V
 2022-05-31 22:38:30 +02:00
florian
ae457a18ad * unified Risc-V 32 and 64 register data file 2022-05-30 21:10:34 +02:00
florian
6a00f9f403 * unified Risc-V 32 and 64 cpubase.pas 2022-05-28 21:15:53 +02:00
florian
ca29df1aa9 * Risc-V: return with mret from interrupt handlers, resolves #39737 2022-05-27 23:33:20 +02:00
florian
27fb9086aa * cleanup: cs_opt_loopunroll is a generic optimization for a long time already 2022-03-08 23:03:18 +01:00
florian
ff3acfb8cd * cleanup of 2.7.0 defines 2021-10-31 13:20:28 +01:00
pierre
e6e49baed1 Add A_CALL to the list of instructions considered as a calljmp, even though it is a pseudo-instruction, fixes a long list of -O3 and -O4 testsuite failures 
git-svn-id: trunk@49468 -
 2021-06-02 20:00:28 +00:00
florian
b9affc3406 * RiscV64: type conversion to 8 bit improved 
git-svn-id: trunk@49015 -
 2021-03-19 17:39:52 +00:00
florian
9ccdf2b3bf * RiscV: unified itcpugas.pas 
git-svn-id: trunk@48960 -
 2021-03-14 10:29:23 +00:00
florian
e047e7db91 + RiscV: initial support of pic generation 
git-svn-id: trunk@48947 -
 2021-03-13 16:18:00 +00:00
florian
d1fb44044f * unified RiscV32 and RiscV64 GAS readers 
git-svn-id: trunk@48894 -
 2021-03-07 08:53:03 +00:00
florian
637976e83f * patch by Marģers to unify internal error numbers, resolves #37888 
git-svn-id: trunk@47103 -
 2020-10-13 19:59:01 +00:00
pierre
d4c9e1f260 Replace outdated cgop2string function by tcgsize2str function from cgbase unit to fix EXTDEBUG cycle on powerpc64le-linux 
git-svn-id: trunk@46689 -
 2020-08-25 13:29:16 +00:00