145 Commits

Author	SHA1	Message	Date
florian	95c2a5a2d7	+ RiscV: support ZMMUL extension	2025-01-26 14:43:57 +01:00
florian	bf41de879a	* factor out TRVCpuAsmOptimizer.OptPass1SLTI	2025-01-22 22:58:34 +01:00
florian	cfc5f17b0d	+ CPURV_HAS_ZICOND	2025-01-20 22:52:23 +01:00
florian	ea9e3e02bd	+ RiscV: write arch attribute	2025-01-17 23:16:38 +01:00
florian	5c6abd2e51	* factor out TRVCpuAsmOptimizer.OptPass1SLTx	2025-01-14 18:53:20 +01:00
florian	f417c87ec8	* RiscV: check for cpu capabilities before using fmv for loading zero	2025-01-12 18:30:32 +01:00
florian	5bb4049737	* remove accidently committed debug statement	2025-01-12 11:32:34 +01:00
florian	dc2c6c8996	* factor out TRVCpuAsmOptimizer.OptPass1Sub	2025-01-12 11:07:29 +01:00
florian	cfee7d07d8	* cleanup	2025-01-11 23:11:41 +01:00
florian	971d97c179	+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0	2025-01-11 21:03:54 +01:00
florian	1202b2612f	+ RiscV: make use of the fl* rd,symbol,rd pseudoinstruction	2025-01-11 14:22:01 +01:00
florian	c3110dfaa9	+ RiscV: make use of the fneg.* instruction	2025-01-09 22:25:26 +01:00
florian	a370b6ff1d	* set is_jmp	2025-01-07 22:51:16 +01:00
Pierre Muller	f2f39d4aaa	Avoid wrong typecast by checking explictly that hp1 is indeed an instruction	2025-01-07 14:40:13 +00:00
florian	e082fe9752	+ OptPass1FSGNJ optimization	2025-01-06 16:00:11 +01:00
florian	7aae7a8d51	+ min/max optimization support for RiscV	2025-01-06 15:21:18 +01:00
florian	b5eaa8555a	* apply OptPass1FOP to FMIN/FMAX as well	2025-01-06 15:21:18 +01:00
florian	2c5a070959	+ random bits for quad support on RiscV	2025-01-06 15:21:18 +01:00
florian	72daf3f556	* RiscV64: optimize 32 bit shift instructions as well	2025-01-04 14:59:00 +01:00
florian	5add799193	* fix trvinlinenode.second_fma	2025-01-01 18:00:15 +01:00
florian	40f9d006d6	* write basic attributes for riscvXX-linux	2024-12-30 15:56:24 +01:00
florian	e30ca27914	* RiscV: write also nopic directive	2024-12-29 18:38:27 +01:00
florian	64e87c87bc	* apply OptPass1OP to SLT/SLTU as well	2024-12-28 23:38:22 +01:00
florian	b7608b045b	* RiscV: push_addr_param unified	2024-12-26 16:49:43 +01:00
florian	9ba3b12eaa	* RiscV: unify push_addr_param	2024-12-25 23:33:11 +01:00
florian	065a81b72c	+ apply OptPass1OP to LA as well	2024-12-25 18:35:46 +01:00
florian	64ba751ef1	* make use of LA pseudo-instruction	2024-12-25 18:35:46 +01:00
florian	57da25581e	+ write .option pic directive if needed	2024-12-25 18:35:46 +01:00
florian	8d0bdf2f16	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
florian	af233b8ef8	* RiscV: floating point registers are saved only for hard float ABIs	2024-12-25 10:16:39 +01:00
florian	49aa141703	* major parts of the RiscV paramgr unified, improves code generation and less failures in RiscV32 regression tests	2024-12-22 22:37:16 +01:00
florian	4bc9f64b70	* continued unification of RiscV paramgr	2024-12-19 22:55:36 +01:00
florian	d33e7920a2	* more RiscV paramgr unification	2024-12-16 22:50:46 +01:00
florian	98b1aee2a5	* more RiscV paramgr unification	2024-12-15 23:01:55 +01:00
florian	f32eaa1564	* skeleton to unify the RiscV paramgr ... * first routines unified	2024-12-15 15:29:05 +01:00
florian	b26c009d90	* apply Addi0Op2Op to more operations	2024-12-13 22:24:57 +01:00
florian	e8144afb6b	* draft of improving Addi0Op2Op	2024-12-04 22:49:48 +01:00
florian	27a0da5a20	* typo corrected	2024-12-02 22:45:34 +01:00
florian	c45d03851a	+ Addi2Nop optimization	2024-12-01 11:21:09 +01:00
florian	4888442fb4	* RiscV: more reliable use_fma	2024-11-18 22:32:55 +01:00
florian	0b49fba637	+ more RiscV extensions ... * make use of F and D extension flags	2024-11-17 15:05:35 +01:00
florian	89b1cdefbe	* more use of OptPass1OP	2024-11-14 22:58:37 +01:00
florian	ccae78f97a	+ RiscV64: apply OptPass1OP also to addiw	2024-11-13 22:56:13 +01:00
florian	1d629270ca	* RiscV64: fix abs(<longint>)	2024-10-14 21:10:10 +02:00
florian	2cfb790eb7	* apply OptPass1FOP to FCVT.*.*	2024-10-13 23:18:38 +02:00
florian	c83a047dda	* extend use of OptPass1FOP	2024-10-11 23:14:03 +02:00
florian	28e1daa8e1	* apply OptPass1FOP to more opcodes	2024-10-06 22:48:00 +02:00
florian	fe4f121721	* generalize FOpFsgnj02FOp optimization	2024-10-05 22:32:17 +02:00
florian	477b9ad556	+ RiscV: FOp.sFsgnj.s02FOp.s optimization	2024-10-04 22:57:26 +02:00
florian	683b566cb7	* improve RiscV assembler optimizer	2024-10-03 22:56:47 +02:00