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r47207 | pierre | 2020-10-26 13:40:45 +0000 (Mon, 26 Oct 2020) | 1 line
Change CLZ support for arm32 minimal CPU to armv5t according to ARM documentation in arminst.dat
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--- Merging r47207 into '.':
U compiler/arm/armins.dat
U compiler/arm/armtab.inc
--- Recording mergeinfo for merge of r47207 into '.':
U .
git-svn-id: branches/fixes_3_2@47923 -
Precisize rules for selection of thumb instructions.
Add short-cut notation support for most simple Thumb2 instructions ( add r1,#4 instead of add r1,r1,#4 ).
git-svn-id: branches/laksen/armiw@29343 -
Move ThumbFunc flag from section to symbol.
Make .w forms optional the other way around. If .w is explicitly put on an instruction the assembler should always chose a wide form.
git-svn-id: branches/laksen/armiw@29341 -
Fixed bug in Mov instruction.
Added initial scanning of IT/LastInIT detection for proper instruction selection.
Disabled "wide" format flag detection again for now.
git-svn-id: branches/laksen/armiw@29338 -
Fixed a bunch of instruction encodings by comparing bulks of handwritten tests to binutils assembled versions.
Fixed emission of regsets of S and D registers above 15.
Fixed assembler reader for RRX shiftmode.
There can be a size postfix after a condition code in UAL assembler syntax. This has been added to the assembler reader.
git-svn-id: branches/laksen/armiw@29277 -
Add some VFP registers.
Rebuilt tables.
Added a lot of VFPv3 and Advanced SIMD(not supported yet) oppostfixes.
Implemented code in aasmcpu to generate binary code from the instructions. Only ARM32 supported so far.
git-svn-id: branches/laksen/armiw@29246 -
