171 Commits

Author	SHA1	Message	Date
florian	b1151ef4ea	+ missing instruction	2025-03-30 20:07:00 +02:00
florian	548e91f104	* fix rol/ror instruction usage and spilling on RiscV	2025-03-28 22:26:59 +01:00
florian	065ddfd8d4	+ RiscV: ROL/ROR code generation support	2025-03-25 22:40:26 +01:00
florian	0785652b55	+ RiscV: handle ror(i)(w) in the assembler optimizer	2025-03-24 23:01:00 +01:00
florian	cafaa9f5b8	+ RiscV: handle rol(w) in the assembler optimizer	2025-03-23 23:04:17 +01:00
florian	310069221a	* comment fixed	2025-03-20 21:55:38 +01:00
florian	61bf79c0ac	+ RiscV: FcmpAndi2Fcmp optimization	2025-03-19 23:00:22 +01:00
florian	860a2d0145	- disable Slti0B2B as well	2025-03-12 22:56:48 +01:00
florian	ad50adf5f3	* some RiscV optimizer improvements and fixes	2025-03-11 22:56:03 +01:00
florian	c7290bfb78	* enclose {$define DEBUG_AOPTCPU} in {$ifdef EXTDEBUG}	2025-03-10 22:50:49 +01:00
florian	1f6ac0609e	+ SltiAndi2Slti optimization	2025-03-09 20:34:21 +01:00
florian	e6d140df80	* make TRVCpuAsmOptimizer.OptPass1SLTIU look further ahead	2025-03-08 23:08:10 +01:00
florian	d91be468da	* fix SltiuAndi2Sltiu optimization	2025-03-07 22:20:46 +01:00
florian	7a19bc012a	+ RiscV: SltiuAndi2Sltiu optimization	2025-03-06 22:59:53 +01:00
florian	783436f2a1	* factor out TRVCpuAsmOptimizer.OptPass1SxxI	2025-03-04 22:52:51 +01:00
florian	2679972f38	* factor out TRVCpuAsmOptimizer.OptPass1SLTIU	2025-03-01 22:24:13 +01:00
florian	70591f6449	* factor out TRVCpuAsmOptimizer.OptPass1Andi	2025-02-27 22:55:35 +01:00
florian	da6c0e919b	+ RiscV: rv32gcb	2025-02-22 21:57:52 +01:00
florian	fecd25bac1	* fix typo ... * properly pass zba, zbb, zbs to march	2025-02-21 22:47:44 +01:00
florian	4664e510e6	* RiscV: handle more instructions in taicpu.spilling_get_operation_type	2025-02-20 23:05:52 +01:00
florian	8e45bb133d	+ RV64GCB CPU type	2025-02-20 22:41:35 +01:00
florian	4427392d56	* RiscV: fix AddiAddi2Addi optimization	2025-02-17 22:35:15 +01:00
florian	9432af9ec6	* RiscV: play safe in taicpu.spilling_get_operation_type	2025-02-16 14:46:39 +01:00
florian	5a07867d20	* RiscV: fixing spilling_get_operation_tpye for LI	2025-02-15 23:08:15 +01:00
florian	b2f6214b33	+ a_bit_scan_reg_reg gets a flag if src cannot be zero: this simplifies the generated code	2025-02-08 14:27:48 +01:00
florian	e17c575123	* properly write RV32E/RV64E architecture tags	2025-01-28 22:38:59 +01:00
florian	95c2a5a2d7	+ RiscV: support ZMMUL extension	2025-01-26 14:43:57 +01:00
florian	bf41de879a	* factor out TRVCpuAsmOptimizer.OptPass1SLTI	2025-01-22 22:58:34 +01:00
florian	cfc5f17b0d	+ CPURV_HAS_ZICOND	2025-01-20 22:52:23 +01:00
florian	ea9e3e02bd	+ RiscV: write arch attribute	2025-01-17 23:16:38 +01:00
florian	5c6abd2e51	* factor out TRVCpuAsmOptimizer.OptPass1SLTx	2025-01-14 18:53:20 +01:00
florian	f417c87ec8	* RiscV: check for cpu capabilities before using fmv for loading zero	2025-01-12 18:30:32 +01:00
florian	5bb4049737	* remove accidently committed debug statement	2025-01-12 11:32:34 +01:00
florian	dc2c6c8996	* factor out TRVCpuAsmOptimizer.OptPass1Sub	2025-01-12 11:07:29 +01:00
florian	cfee7d07d8	* cleanup	2025-01-11 23:11:41 +01:00
florian	971d97c179	+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0	2025-01-11 21:03:54 +01:00
florian	1202b2612f	+ RiscV: make use of the fl* rd,symbol,rd pseudoinstruction	2025-01-11 14:22:01 +01:00
florian	c3110dfaa9	+ RiscV: make use of the fneg.* instruction	2025-01-09 22:25:26 +01:00
florian	a370b6ff1d	* set is_jmp	2025-01-07 22:51:16 +01:00
Pierre Muller	f2f39d4aaa	Avoid wrong typecast by checking explictly that hp1 is indeed an instruction	2025-01-07 14:40:13 +00:00
florian	e082fe9752	+ OptPass1FSGNJ optimization	2025-01-06 16:00:11 +01:00
florian	7aae7a8d51	+ min/max optimization support for RiscV	2025-01-06 15:21:18 +01:00
florian	b5eaa8555a	* apply OptPass1FOP to FMIN/FMAX as well	2025-01-06 15:21:18 +01:00
florian	2c5a070959	+ random bits for quad support on RiscV	2025-01-06 15:21:18 +01:00
florian	72daf3f556	* RiscV64: optimize 32 bit shift instructions as well	2025-01-04 14:59:00 +01:00
florian	5add799193	* fix trvinlinenode.second_fma	2025-01-01 18:00:15 +01:00
florian	40f9d006d6	* write basic attributes for riscvXX-linux	2024-12-30 15:56:24 +01:00
florian	e30ca27914	* RiscV: write also nopic directive	2024-12-29 18:38:27 +01:00
florian	64e87c87bc	* apply OptPass1OP to SLT/SLTU as well	2024-12-28 23:38:22 +01:00
florian	b7608b045b	* RiscV: push_addr_param unified	2024-12-26 16:49:43 +01:00