florian
b2f5f6ac7d
+ RiscV32: use sext.b if available
2025-02-24 23:05:49 +01:00
florian
da6c0e919b
+ RiscV: rv32gcb
2025-02-22 21:57:52 +01:00
florian
95c2a5a2d7
+ RiscV: support ZMMUL extension
2025-01-26 14:43:57 +01:00
florian
cfc5f17b0d
+ CPURV_HAS_ZICOND
2025-01-20 22:52:23 +01:00
florian
971d97c179
+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0
2025-01-11 21:03:54 +01:00
Pierre Muller
a9ab15c60d
Fix compilation of riscv32 compiler
2025-01-10 12:10:02 +00:00
florian
c3110dfaa9
+ RiscV: make use of the fneg.* instruction
2025-01-09 22:25:26 +01:00
florian
b7608b045b
* RiscV: push_addr_param unified
2024-12-26 16:49:43 +01:00
florian
9ba3b12eaa
* RiscV: unify push_addr_param
2024-12-25 23:33:11 +01:00
florian
b4a83e29a4
* fixes RiscV32 building
2024-12-25 22:48:40 +01:00
florian
57da25581e
+ write .option pic directive if needed
2024-12-25 18:35:46 +01:00
florian
8d0bdf2f16
+ RiscV: vector registers
2024-12-25 10:34:46 +01:00
florian
49aa141703
* major parts of the RiscV paramgr unified, improves code generation and less failures in RiscV32 regression tests
2024-12-22 22:37:16 +01:00
florian
4bc9f64b70
* continued unification of RiscV paramgr
2024-12-19 22:55:36 +01:00
florian
d33e7920a2
* more RiscV paramgr unification
2024-12-16 22:50:46 +01:00
florian
98b1aee2a5
* more RiscV paramgr unification
2024-12-15 23:01:55 +01:00
florian
f32eaa1564
* skeleton to unify the RiscV paramgr
...
* first routines unified
2024-12-15 15:29:05 +01:00
florian
0b49fba637
+ more RiscV extensions
...
* make use of F and D extension flags
2024-11-17 15:05:35 +01:00
florian
159d97e864
* Risc-V: make use of sext.h instruction if available
2024-08-15 21:53:04 +02:00
florian
a53eb8b230
+ Risc-V: make use of zext.h if available
2024-08-14 22:37:26 +02:00
florian
0366df9fbd
+ Zb* cpu capabilities
2024-08-11 22:47:29 +02:00
florian
d4816d12f7
* Risc-V 32 has also a GC variant
2024-08-08 22:58:47 +02:00
florian
3e6cd16bb5
+ Risc-V 32: tcpuparamanager.get_saved_registers_int
2024-08-05 22:37:18 +02:00
florian
4afb07cc5e
+ Risc-V 32: tcpuparamanager.get_saved_registers_fpu
2024-08-04 23:03:44 +02:00
florian
6d157b5bf0
+ Risc-V 32: optimize QWord(1) shl ...
2024-07-28 21:17:25 +02:00
florian
d270c2ccdd
* better zero extension for Risc-V32
2024-07-28 16:42:32 +02:00
florian
1737035501
+ riscv32: trv32shlshrnode.second_64bit
2024-07-27 19:48:16 +02:00
Michael Ring
14b3c11c0d
Initial support for esp32-c6-s2-s3. Support for idf versions 5.0.6 and 5.2.1
2024-07-18 20:16:04 +00:00
florian
39f7172ee8
* do no generated debug comment in assembler output of RiscV if not requested
2024-05-25 20:16:42 +02:00
florian
0a88683310
+ do do_consttovar on RiscV
2024-05-25 20:09:02 +02:00
florian
fbf20eee31
+ check for tf_init_final_units_by_calls in trv32nodeutils.insert_init_final_table
2024-05-25 19:28:50 +02:00
ccrause
c86e7b43b4
Add insert_init_final_table method
2024-05-25 17:26:15 +00:00
florian
f49da05633
* unified g_concatcopy_move
2024-05-15 22:52:24 +02:00
Pierre Muller
acf5675a90
Change AVOID_OVERFLOW to avoid warning about inequality being always true
2023-10-26 07:47:10 +00:00
Pierre Muller
b521ac967f
Fix possible overflow in riscv32 compiler
2023-10-26 01:02:20 +00:00
florian
dd586da709
* formatting
2023-08-26 22:14:36 +02:00
Interferon
c482bafdaf
There is code in the register allocator to restrict register allocation to the
...
first 16 registers in RISC-V RVE and RVEC modes. However, there was still
code in tcpuparamanager.create_paraloc_info_intern that allowed the allocation
of up to register X17 in RVE and RVEC modes. Modified this function to
take the processor mode into account and restrict it to X0..X15 in RVE and RVEC modes.
Also put conditional code in setjump.inc assembler code to only set the first
16 registers in RVE and RVEC modes.
The entire embedded-riscv32 RTL can now compile successfuly in RVEC mode.
2023-08-26 22:12:00 +02:00
Interferon
8382c6f586
Added generic WCH32Vx RISC-V processor types using memory size suffixes
...
Modified low-level startup code for RISCV32 embedded microcontrollers to
allow user code override of reset handlers for non-power-up reset events
as well as enabling user code override handlers for all 255 possible
interrupt vectors.
Separated out the low-level startup memory init into a callable procedure
to allow users that have caught reset events to init memory again if needed.
Signed-off-by: Interferon <brspm2@pinnaclesimulation.com>
2023-08-26 22:12:00 +02:00
florian
63199a0966
* memory sizes updated
2023-02-12 20:55:38 +01:00
florian
e9ec4a8bb3
* more riscv32-freertos-esp32c3 stuff added
2023-01-29 19:30:11 +01:00
florian
bedd4edc72
+ first work for esp32-c3 support
2023-01-28 21:28:19 +01:00
Jeppe
c83e6c34a9
riscv32: Fix 64bit comparisons
...
- Code taken from MIPS backend
- Removed some unused code generated for RV32 64bit integer ops
2022-10-16 17:37:53 +02:00
florian
e2a26ecece
* fixes tcg64frv.a_op64_const_reg_reg based on the analysis of Bart B, resolves #39953
2022-10-13 23:16:19 +02:00
florian
19ad26afd8
* Riscv32 and Riscv64 on linux: enable safecall support
2022-07-22 22:56:21 +02:00
florian
a16f35dcb1
+ support RV32E Extension
2022-07-17 22:14:13 +02:00
Jeppe
f5cf8956c5
riscv: Merge stack code, fix interrupted code
...
- Stack pointer is kept below register save area. This ensures that
registers are not overwritten by interrupt handlers.
- RV32 and 64 code is merged to base class.
2022-07-02 15:07:42 +02:00
Jeppe
37b5147b19
riscv32: Fix potential FP proc_exit bug
2022-07-02 15:07:42 +02:00
florian
def37052f1
+ RiscV32: patch by kupferstecher: compiler support of CH32V30*, part of #39777
2022-06-12 23:01:39 +02:00
florian
ae457a18ad
* unified Risc-V 32 and 64 register data file
2022-05-30 21:10:34 +02:00
florian
6a00f9f403
* unified Risc-V 32 and 64 cpubase.pas
2022-05-28 21:15:53 +02:00
